MSC7118 datasheet(45/60 Pages) FREESCALE

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Hardware Design Considerations

MSC7118 Low-Cost 16-bit DSP with DDR Controller Data Sheet, Rev. 7

Freescale Semiconductor

3.2.2.5

Case 5 (not recommended for new designs)

The power-up sequence is as follows:

Turn on the VDDIO (3.3 V) supply first.

Turn on the VDDM (2.5 V) supply second.

Turn on the VDDC (1.2 V) supply third.

Turn on the VREF (1.25 V) supply fourth (last).

Note:

Make sure that the time interval between the ramp-up of VDDIO and VDDM is less than 10 ms.

The power-down sequence is as follows:

Turn off the VREF (1.25 V) supply first.

Turn off the VDDC (1.2 V) supply second.

Turn off the VDDM (2.5 V) supply third.

Turn of the VDDIO (3.3 V) supply fourth (last).

Use the following guidelines:

•

Make sure that the time interval between the ramp-down of VDDIO and VDDM is less than 10 ms.

•

Make sure that the time interval between the ramp-up or ramp-down for VDDC and VDDM is less than 2 ms for

power-up and power-down.

•

Refer to Figure 30 for relative timing for power sequencing case 5.

Note:

Cases 1, 2, 3, and 4 are recommended for system design. Designs that use Case 5 may have large current spikes on

the VDDM supply at startup and is not recommended for most designs. If a design uses case 5, it must accommodate

the potential current spikes. Verify risks related to current spikes using actual information for the specific application.

Figure 30. Voltage Sequencing Case 5

Time

Ramp-down

Ramp-up

VDDIO = 3.3 V

VDDM = 2.5 V

VDDC = 1.2 V

VREF = 1.25 V

<10 ms

<2 ms

<10 ms

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