MSC7119 datasheet(43/60 Pages) FREESCALE

部品番号	MSC7119

部品情報	Low-Cost 16-bit DSP with DDR Controller and 10/100 Mbps Ethernet MAC

PDF	60 Pages

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Hardware Design Considerations

MSC7119 Data Sheet, Rev. 8

Freescale Semiconductor

3.2.2.1

Case 1

The power-up sequence is as follows:

Turn on the VDDIO (3.3 V) supply first.

Turn on the VDDC (1.2 V) supply second.

Turn on the VDDM (2.5 V) supply third.

Turn on the VREF (1.25 V) supply fourth (last).

The power-down sequence is as follows:

Turn off the VREF (1.25 V) supply first.

Turn off the VDDM (2.5 V) supply second.

Turn off the VDDC (1.2 V) supply third.

Turn of the VDDIO (3.3 V) supply fourth (last).

Use the following guidelines:

•

Make sure that the time interval between the ramp-down of VDDIO and VDDC is less than 10 ms.

•

Make sure that the time interval between the ramp-up or ramp-down for VDDC and VDDM is less than 10 ms for

power-up and power-down.

•

Refer to Figure 30 for relative timing for power sequencing case 1.

Figure 30. Voltage Sequencing Case 1

Time

Ramp-down

Ramp-up

VDDIO = 3.3 V

VDDM = 2.5 V

VDDC = 1.2 V

VREF = 1.25 V

<10 ms

MSC7119 データシート(PDF) 43 Page - Freescale Semiconductor, Inc