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HD404612FS データシート(PDF) 21 Page - Renesas Technology Corp

部品番号 HD404612FS
部品情報  4-Bit Single-Chip Microcomputer
PDF  91 Pages
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メーカー  RENESAS [Renesas Technology Corp]
ホームページ  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

HD404612FS データシート(HTML) 21 Page - Renesas Technology Corp

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HD404618 Series
19
Table 3 Interrupt Processing and Activation Conditions
Interrupt Source
Interrupt
Control Bit
INT
0
INT
1
Timer A
Timer B
Timer C
Serial
IE
1111
11
IF0·
IM0
1000
00
IF1·
IM1
*
100
00
IFTA·
IMTA
**
10
00
IFTB·
IMTB
***
10
0
IFTC·
IMTC ****
10
IFS·
IMS
****
*
1
Note: Bits marked by * can be either 0 or 1. Their values have no effect on operation.
Instruction cycles
12
3
4
5
6
Instruction
execution*
IE reset
Interrupt
acceptance
Execution of JMPL
instruction at vector address
Execution of
instruction at
start address
of interrupt
routine
Vector address
generation
Note: * The stack is accessed and the IE reset after the instruction
is executed, even if it is a two-cycle instruction.
Stacking
Figure 8 Interrupt Processing Sequence



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