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HD404618TF データシート(PDF) 86 Page - Renesas Technology Corp |
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HD404618TF データシート(HTML) 86 Page - Renesas Technology Corp |
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86 / 91 page  HD404618 Series 84 During Transmit Clock Input Item Symbol Pin(s) Min Typ Max Test Condition Unit Notes Transmit clock cycle time t Scyc SCK 1— — t cyc /tsubcyc 1, 3 Transmit clock high width t SCKH SCK 0.5 — — t Scyc 1 Transmit clock low width t SCKL SCK 0.5 — — t Scyc 1 Transmit clock rise time t SCKr SCK — — 200 ns 1 Transmit clock fall time t SCKf SCK — — 200 ns 1 Serial output data delay time t DSO SO — — 500 Load shown in figure 54 ns 1 Serial input data setup time t SSI SI 300 — — ns 1 Serial input data hold time t HSI SI 300 — — ns 1 Transmit clock completion detect time t SCKHD SCK 1— — t cyc /tsubcyc 1, 2, 3 Notes: 1. See figure 53. 2. The transmit clock completion detect time is the high level period after eight transmit clock pulses have been input. The serial interrupt request flag is not set if the next transmit clock is input before the transmit clock completion detect time has passed. 3. The unit t subcyc applies when the MCU is in subactive mode. t subcyc = 244.14 µs (32.768-kHz crystal oscillator) TONEC TONER R = 100 k Ω L R = 100 k Ω L Figure 48 Tone Output Load Circuit |
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