STV0299B datasheet(11/36 Pages) STMICROELECTRONICS

11 / 36 page

STV0299B

11/36

For the “Unmodulated Tone Burst” Port CTRL 2 is

set to 0 and, only one byte, of value 00h is sent.

The parity bit is still 1, and as a result, the signal is

continuous

train

12.5 ms.

When

the

modulation is active, the DiSEqC output is driven

alternatively to VDD and VSS levels. The DiSEqC

and Lock Control, DiSEqC FIFO and DiSEqC

Status Registers are in Addresses 08, 09 and

0Ah.

Figure 5:

Schematic showing Bit Transmission

Table 3:

Note:

Byte to transfer in DiSEqC mode.

In mode PortCtrl (1:0)=10, the F22/DiSEqC pin returns to High -2 mode once the transmission is completed.

4.1.13 Standby Mode

A low power consumption mode (standby mode)

can be implemented (in this mode, fM_CLK = 0). In

standby mode, the I2C decoder still operates, but

with some restrictions (see Sections 4.1.4 and

4.1.5).

Standby mode can be initiated or stopped by I2C

bus commands as described in MCR Register 02.

At power-on, the circuit starts to operate in

standby mode when the STDBY pin (pin 42) is

tied

VDD.

This

guarantees

low

power

consumption

for

the

stand-alone

modules

(PCMCIA size front-end modules) before any

command

initiated.

After

the

power-on

sequence, the standby mode is entirely controlled

via MCR Register (02).

Idle

11 Periods

Next bit

Transmission of 1’s

Transmission of 0’s:

a) PortCtrl2 = 1

b) PortCtrl2 = 0

PortCtrl (1:0)

PortCtrl (2)

FIFO

Output

empty

DATA = 00

Unmodulated tone burst

DATA = FFor00

Modulated tone burst

Note 1

DiSEqC signal

Continuous tone

STV0299B データシート(PDF) 11 Page - STMicroelectronics

STV0299B データシート(HTML) 11 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36

データシートダウンロード