M32CSLASH8B datasheet(241/406 Pages) RENESAS

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M32C/8B Group

17. Serial Interfaces

Preliminary specification

Specifications in this manual are tentative and subject to change.

REJ09B0450-0050 Rev.0.50 Oct 31, 2008

Page 224 of 385

17.1.3

Special Mode 1 (I2C Mode)

In I2C mode, the simplified I2C helps to communicate with external devices.

Table 17.6 lists specifications of I2C mode. Tables 17.7 and 17.8 list register settings. Tables 17.9 and 17.10 list

individual functions in I2C mode. Table 17.11 lists pin settings. Figure 17.23 shows a block diagram of I2C

mode. Figure 17.24 shows a transfer timing to the UiRB register (i = 0 to 4) and interrupt timing.

Table 17.6

I2C Mode Specifications

NOTES:

1. Bits CNT3 to CNT0 in the TCSPR register select no division (n = 0) or divide-by-2n (n = 1 to 15).

2. If an external clock is selected, satisfy the conditions while an “H” signal is applied to the SCLi pin.

3. If an overrun error occurs, a read from the UiRB register returns undefined values.

Item

Specification

Data format

• Data length: 8 bits long

Baud rate

• In master mode

When the CKDIR bit in the UiMR register (i = 0 to 4) is set to 0 (internal clock):

fj / (2 (m + 1))

fj = f1, f8, f2n(1) m: setting value of the UiBRG register (00h to FFh)

• In slave mode

When the CKDIR bit is set to 1 (external clock): input from the SCLi pin

Transmit start condition

To start transmit operation, all of the following must be met(2):

• Set the TE bit in the UiC1 register to 1 (transmit operation enabled)

• The TI bit in the UiC1 register is 0 (data in the UiTB register)

Receive start condition

To start receive operation, all of the following must be met(2):

• Set the TE bit to 1 (transmit operation enabled)

• The TI bit is 0 (data in the UiTB register)

• Set the RE bit in the UiC1 register to 1 (receive operation enabled)

Interrupt request generation

timing

• Start condition detection

• Stop condition detection

• ACK (Acknowledge) detection

• NACK (Not-Acknowledge) detection

Error detection

• Overrun error(3)

Overrun error occurs when the 8th bit of the next data is received before reading the

UiRB register

Selectable function

• Arbitration lost detect timing

Update timing of the ABT bit in the UiRB register (i = 0 to 4) can be selected.

• SDAi digital delay

No digital delay or 2 to 8 cycle delay of the UiBRG count source can be selected.

• Clock phase setting

Clock delay or no clock delay can be selected.

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