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H8SX1663 データシート(PDF) 464 Page - Renesas Technology Corp |
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H8SX1663 データシート(HTML) 464 Page - Renesas Technology Corp |
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464 / 1158 page  Section 8 Data Transfer Controller (DTC) Rev.1.00 Jun. 07, 2006 Page 412 of 1102 REJ09B0294-0100 Clock Address DTC activation request DTC request BB W R W Clock Address DTC activation request DTC request WW L R W Clock Address DTC activation request DTC request BB L W R W [Example 1: When an odd address and even address are specified in SAR and DAR, respectively, and when the data size of transfer is specified as word] [Example 2: When an odd address and address 4n are specified in SAR and DAR, respectively, and when the data size of transfer is specified as longword] [Example 3: When address 4n + 2 and address 4n are specified in SAR and DAR, respectively, and when the data size of transfer is specified as longword] Vector read Transfer information read Data transfer Transfer information write Vector read Transfer information read Data transfer Transfer information write Vector read Transfer information read Data transfer Transfer information write Figure 8.5 Bus Cycle Division Example |
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