H8SX1663 datasheet(679/1158 Pages) RENESAS

部品番号	H8SX1663

部品情報	Renesas 32-Bit CISC Microcomputer H8SX Family / H8SX/1600 Series

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Section 12 8-Bit Timers (TMR)

Rev.1.00 Jun. 07, 2006 Page 627 of 1102

REJ09B0294-0100

12.5.4

Timing of Counter Clear by Compare Match

TCNT is cleared when compare match A or B occurs, depending on the settings of the bits

CCLR1 and CCLR0 in TCR. Figure 12.11 shows the timing of this operation.

H'00

Compare match

signal

TCNT

Figure 12.11 Timing of Counter Clear by Compare Match

12.5.5

Timing of TCNT External Reset*

TCNT is cleared at the rising edge or high level of an external reset input, depending on the

settings of bits CCLR1 and CCLR0 in TCR. The clear pulse width must be at least 2 states. Figure

12.12 and Figure 12.13 shows the timing of this operation.

Note: * Clearing by an external reset is available only in units 0 and 1.

Clear signal

External reset

input pin

TCNT

H'00

N – 1

Figure 12.12 Timing of Clearance by External Reset (Rising Edge)

Clear signal

External reset

input pin

TCNT

H'00

N – 1

Figure 12.13 Timing of Clearance by External Reset (High Level)

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