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SH7713 データシート(PDF) 94 Page - Renesas Technology Corp |
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SH7713 データシート(HTML) 94 Page - Renesas Technology Corp |
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94 / 904 page  Section 2 CPU Rev.1.50 Aug. 30, 2006 Page 54 of 860 REJ09B0288-0150 Type Kinds of Instruction Op Code Function Number of Instructions 9 BF Conditional branch, delayed conditional branch (T = 0) 11 BT Conditional branch, delayed conditional branch (T = 1) BRA Unconditional branch BRAF Unconditional branch BSR Branch to subroutine procedure BSRF Branch to subroutine procedure JMP Unconditional branch JSR Branch to subroutine procedure Branch instructions RTS Return from subroutine procedure 15 CLRT T bit clear 75 CLRMAC MAC register clear CLRS S bit clear LDC Load into control register LDS Load into system register LDTLB PTEH/PTEL load into TLB NOP No operation PREF Data prefetch to cache RTE Return from exception handling SETS S bit setting SETT T bit setting SLEEP Transition to power-down mode STC Store from control register STS Store from system register System control instructions TRAPA Trap exception handling Total: 68 188 The instruction code, operation, and number of execution states of the CPU instructions are shown in the following tables, classified by instruction type, using the format shown below. |
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