7220 datasheet(86/303 Pages) RENESAS

86 / 303 page

2-59

7220 Group User’s Manual

2.8 Multi-master I2C-BUS interface

(3)

START/STOP condition detect conditions

The START/STOP condition detect conditions are shown in Figure 2.8.11 and Table 2.8.3. Only when

the 3 conditions of Table 10 are satisfied, a START/STOP condition can be detected.

Note: When a STOP condition is detected in the slave mode (MST = 0), an interrupt request signal

“IICIRQ” is generated to the CPU.

Hold time

Setup

time

SCL

SDA

(START condition)

SDA

(STOP condition)

SCL release time

Hold time

Setup

time

Fig. 2.8.11 START condition/STOP condition detect timing diagram

Table 2.8.3

START condition/STOP condition detect conditions

Standard clock mode

6.5

µ s (26 cycles) < SCL release time

3.25

µ s (13 cycles) < Setup time

3.25

µ s (13 cycles) < Hold time

High-speed clock mode

1.0

µ s (4 cycles) < SCL release time

0.5

µ s (2 cycles) < Setup time

0.5

µ s (2 cycles) < Hold time

Note: Absolute time at

f = 4 MHz. The value in parentheses denotes the number of f cycles.

FUNCTIONAL DESCRIPTION

7220 データシート(PDF) 86 Page - Renesas Technology Corp

7220 データシート(HTML) 86 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

データシートダウンロード