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7906 データシート(PDF) 49 Page - Renesas Technology Corp |
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7906 データシート(HTML) 49 Page - Renesas Technology Corp |
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49 / 531 page  RESET 7906 Group User’s Manual Rev.2.0 3-6 3.3 State of internal area Figure 3.3.1 shows the state of CPU registers immediately after reset. Figures 3.3.2 to 3.3.9 show the state of the SFR and internal RAM areas immediately after reset. 3.3 State of internal area Fig. 3.3.1 State of CPU registers immediately after reset 0 1 ? : “0” immediately after reset. : “1” immediately after reset. : Undefined immediately after reset. Data bank register (DT) 0016 b7 b0 Program bank register (PG) 0016 b7 b0 Program counter (PC) Contents at address FFFE16 Contents at address FFFF16 b7 b0 b15 b8 Direct page register 0 (DPR0) 0016 b7 b0 0016 b15 b8 Processor status register (PS) 0 0 00 0 0 1 b7 b0 b15 b8 NV mx D IZ C IPL ? ?? ? Stack pointer (S) FF16 b7 b0 0F16 b15 b8 Index register Y (Y) ? b7 b0 ? b15 b8 Index register X (X) ? b7 b0 ? b15 b8 Accumulator B (B) ? b7 b0 ? b15 b8 Accumulator A (A) ? b7 b0 ? b15 b8 Register name State immediately after reset : “0” immediately after reset. Fix this bit to “0.” Direct page register i (DPRi) ? b7 b0 ? b15 b8 (i = 1 to 3) 0 0 0 0 0 0 |
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