TAS3218IPZP datasheet(38/79 Pages) TI

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DO0

DO1

DO2

DO3

DO4

DO5

DO6

DO7

DO8

Audio_out1 Audio_out2 Audio_out3 Audio_out4

SPDIF(L)

SPDIF(R)

DAC

(TDM)

Audio _out5 Audio_out6 Audio_out7

Audio_out8

Ext_mem

nd Gen)

SDOUT1(L)

SDOUT1( R)

SDOUT2(L)

SDOUT2( R)

Inside core

Outside core

Micro Data

48 -bit

Datapath

28 x 48-bit Multiplier

76-bit Accumulator

Coef RAM

(1 K x 28 )

Data RAM

(768 x 48 )

Program RAM

(3 .25 K x 55 )

DSP

Controller

Memory

Interface

Delay

Memory

(17408 x 24 )

8 -bit MCU

(8051 )

Internal

Data RAM

(256 x 8 )

External

Data RAM

(2 K x 8 )

Program RAM

(16 K x 8 )

DSP

Delay

Control

MICRO

Delay Memory

TAS3218

SLES235 – JULY 2008 ....................................................................................................................................................................................................... www.ti.com

Figure 28. DSP Output Register Configuration

Memory size K = 1024

Figure 29. DSP, MCU, and Memory Interfaces

The Delay Memory Interface (DMIF) is the interface block between the DSP core and the delay memory. The

DMIF blocks primary purpose is to keep track of twenty four sets of delay memory pointers that are initially set up

by the micro controller through an I2C command(s). Eight of the pointers are used to write/retrieve 48-bit data

(full-precision intermediate) and the other sixteen for 24-bit data (post quantized). Thus to support 48-bit word

reverb delay, two RAM locations must be used.

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