1

10

100

1k

10k

100k

Rg (Ohm)

40

60

80

100

120

140

160

180

200

En (

µV)

Vs= 14.4 V

RL= 4 Ohm

22 - 22K Hz lin.

”A” wgtd

Figure 9: Output Noise vs. Source Resistance

Ptot (W)

Figure 10: Power Dissipation & Efficiency vs.

Output Power

APPLICATION HINTS (ref. to the circuit of fig. 1)

BIASING AND SVR

As shown by fig. 11, all the TDA7383’s main sec-

tions, such as INPUTS, OUTPUTS AND AC-GND

(pin 16) are internally biased at half Supply Volt-

age level (Vs/2), which is derived from the Supply

Voltage Rejection (SVR) block. In this way no cur-

rent flows through the internal feedback network.

The AC-GND is common to all the 4 amplifiers

and represents the connection point of all the in-

verting inputs.

Both individual inputs and AC-GND are con-

nected to Vs/2 (SVR) by means of 100K

Ω resis-

tors.

To ensure proper operation and high supply volt-

age rejection, it is of fundamental importance to

provide a good impedance matching between IN-

PUTS and AC-GROUND terminations. This im-

TO CARRY THE SAME NOMINAL VALUE AND

THEIR TOLERANCE SHOULD NEVER EXCEED

±10 %.

Besides its contribution to the ripple rejection, the

SVR capacitor governs the turn ON/OFF time se-

quence and, consequently, plays an essential role

in the pop optimization during ON/OFF transients.

To conveniently serve both needs, ITS MINIMUM

RECOMMENDED VALUE IS 10

µF.

+

-

0.1

µF

C1

÷ C4

+

-

8K

Ω

8K

Ω

400

Ω

400

Ω

100K

Ω

100K

Ω

70K

Ω

IN

D95AU302

TOWARDS

OTHER CHANNELS

10K

Ω

10K

Ω

47

µF

C6

0.1

µF

C5

SVR

AC_GND

Figure 11: Input/OutputBiasing.

TDA7383

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