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Altera Corporation

747

Classic EPLD Family Data Sheet

f For more information, see the MAX+PLUS II Programmable Logic

Development System & Software Data Sheet.

Functional

Description

The Classic architecture includes the following elements:

Macrocells

Programmable registers

Output enable/clock select

Feedback select

Macrocells

Classic macrocells, shown in Figure 1, can be individually configured for

both sequential and combinatorial logic operation. Eight product terms

form a programmable-AND array that feeds an OR gate for combinatorial

logic implementation. An additional product term is used for

asynchronous clear control of the internal register; another product term

implements either an output enable or a logic-array-generated clock.

Inputs to the programmable-AND array come from both the true and

complement signals of the dedicated inputs, feedbacks from I/O pins that

are configured as inputs, and feedbacks from macrocell outputs. Signals

from dedicated inputs are globally routed and can feed the inputs of all

device macrocells. The feedback multiplexer controls the routing of

feedback signals from macrocells and from I/O pins. For additional

information on feedback select conﬁgurations, see Figure 3 on page 749.

Figure 1. Classic Device Macrocell

To Logic Array

Output Enable/Clock Select

Global

Clock

CLK

Programmable

Input, I/O, and

Macrocell

Feedbacks

Logic Array

Feedback

Select

CLR

Asynchronous Clear

VCC

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