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EPLD データシート(PDF) 39 Page - Altera Corporation

部品番号 EPLD
部品情報  The Altera Classic device family offers a solution to high-speed, lowpower logic integration. Fabricated on advanced CMOS technology
PDF  42 Pages
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メーカー  ALTERA [Altera Corporation]
ホームページ  http://www.altera.com
Logo ALTERA - Altera Corporation

EPLD データシート(HTML) 39 Page - Altera Corporation

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Altera Corporation
783
Classic EPLD Family Data Sheet
Tables 28 through 31 show the timing parameters for EP1810-20,
EP1810-25, EP1810-35, and EP1810-45 devices.
Table 28. EP1810-20 & EP1810-25 External Timing Parameters
Note (1)
Symbol
Parameter
Conditions
EP1810-20 EP1810-25
Non-Turbo
Adder
Unit
Min Max Min Max
(2)
tPD1
Input to non-registered output
C1 = 35 pF
20.0
25.0
25.0
ns
tPD2
I/O input to non-registered output
C1 = 35 pF
22.0
28.0
25.0
ns
tSU
Global clock setup time
13.0
17.0
25.0
ns
tH
Global clock hold time
0.0
0.0
0.0
ns
tCH
Global clock high time
8.0
10.0
0.0
ns
tCL
Global clock low time
8.0
10.0
0.0
ns
tCO1
Global clock to output delay
C1 = 35 pF
15.0
18.0
0.0
ns
tCNT
Minimum global clock period
(3)
20.0
25.0
0.0
ns
fCNT
Maximum internal frequency
(3)
50.0
40.0
0.0
MHz
tASU
Array clock setup time
8.0
10.0
25.0
ns
tAH
Array clock hold time
8.0
10.0
0.0
ns
tACO1
Array clock to output delay
C1 = 35 pF
20.0
25.0
25.0
ns
tODH
Output data hold time after clock
C1 = 35 pF
(4)
1.0
1.0
0.0
ns
tACNT
Array clock maximum clock period
(3)
20.0
25.0
0.0
ns
fACNT
Maximum internal array clock
frequency
(3)
50.0
40.0
0.0
ns
fMAX
Maximum clock frequency
(5)
62.5
50.0
0.0
MHz
Table 29. EP1810-20 and EP1810-25 Internal Timing Parameters
Symbol
Parameter
Conditions
EP1810-20 EP1810-25
Non-Turbo
Adder
Unit
Min Max Min Max
(2)
tIN
Input pad and buffer delay
5.0
7.0
0.0
ns
tIO
I/O input pad and buffer delay
2.0
3.0
0.0
ns
tLAD
Logic array delay
9.0
12.0
25.0
ns
tOD
Output buffer and pad delay
C1 = 35 pF
6.0
6.0
0.0
ns
tZX
Output buffer enable delay
C1 = 35 pF
6.0
6.0
0.0
ns
tXZ
Output buffer disable delay
C1 = 5 pF
(6)
6.0
6.0
0.0
ns
tSU
Register setup time
8.0
10.0
0.0
ns
tH
Register hold time
5.0
10.0
0.0
ns
tIC
Array clock delay
9.0
12.0
25.0
ns
tICS
Global clock delay
4.0
5.0
0.0
ns
tFD
Feedback delay
3.0
3.0
–25.0
ns
tCLR
Register clear time
9.0
12.0
25.0
ns



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