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U4091BM-R データシート(PDF) 8 Page - ATMEL Corporation

部品番号 U4091BM-R
部品情報  Programmable Telephone Audio Processor
PDF  38 Pages
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メーカー  ATMEL [ATMEL Corporation]
ホームページ  http://www.atmel.com
Logo ATMEL - ATMEL Corporation

U4091BM-R データシート(HTML) 8 Page - ATMEL Corporation

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8
4872A–CORD–08/05
U4091BM-R
7.
Clock Output Divider Adjustment
The pin OSCOUT is a clock output which is derived from the crystal oscillator. It can be used to
drive a microcontroller or another remote component and thereby reduces the number of crys-
tals required. The oscillator frequency can be divided by 1, 8, 16, or 32. During power-on reset,
the divider will be reset to 1 until it is changed by setting the serial bus.
8.
Serial Bus Interface
The circuit is controlled by an external microcontroller through the serial bus.
The serial bus is a bi-directional system consisting of a single-directional clock line (SCL) which
is always driven by the microcontroller, and a bi-directional data-signal line. It is driven by the
microcontroller as well as by the U4091BM-R (see Figure 20-1 on page 37).
The serial bus requires external pull-up resistors as only pull-down transistors (pin SDA) are
integrated.
8.1
WRITE
The data is a 12-bit word:
A0-A3: address of the destination register (0 to 15)
D0-D7: content of the register
The data line must be stable when the clock is high. Data must be shifted serially. After 12 clock
periods, the write indication is sent. Then, the transfer to the destination register is (internally)
generated by a strobe signal transition of the data line when the clock is high.
8.2
READ
There is a normal and a fast-read cycle.
In the normal read cycle, the microcontroller sends a 4-bit address followed by the read indica-
tor, then an 8-bit word is read out. The U4091BM-R drives the data line.
The fast read cycle is indicated by a strobe signal. With the following two clocks the U4091BM-R
reads out the status bits RFDO and LIDET which indicate that a ringing signal or a line signal is
present (see Figure 10-1 on page 11, Figure 10-2 on page 11 and Figure 10-3 on page 11).
Table 6-1.
Threshold Level
RINGTH[0:3]
V
RING
07V
15
22V
Step
1V
Table 7-1.
Clock Output
CLK[0:1]
Divider
Frequency
0
1
3.58 MHz
1
8
447 kHz
2
16
224 kHz
3
32
112 kHz



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