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CMS3216LAH データシート(PDF) 3 Page - FIDELIX

部品番号 CMS3216LAH
部品情報  32M(2Mx16) Low Power SDRAM
PDF  46 Pages
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メーカー  FIDELIX [FIDELIX]
ホームページ  http://www.fidelix.co.kr
Logo FIDELIX - FIDELIX

CMS3216LAH データシート(HTML) 3 Page - FIDELIX

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Rev0.2, Jan. 2007
CMS3216LAx-75xx
Features
- Functionality
- Standard SDRAM Functionality
- Programmable burst lengths : 1, 2, 4, 8, or full page
- JEDEC Compatibility
-Low Power Features
- Low voltage power supply : 2.5V/3.0V
- Auto TCSR(Temperature Compensated Self Refresh)
- Partial Array Self Refresh power-saving mode
- Deep Power Down Mode
- Driver Strength Control
- Operating Temperature Ranges:
- Special (-10℃ to +60℃)
- Commercial (0℃ to +70℃)
- Extended (-25℃ to +85℃)
- Industrial (-40℃ to +85℃)
- LVCMOS Compatible IO Interface
- 54ball FBGA with 0.8mm ball pitch
- CMS3216LAF : Normal
- CMS3216LAG : Pb-Free
- CMS3216LAH : Pb-Free & Halogen Free
Functional Description
The CMS3216LAx-xxxx family is high-performance CMOS
Dynamic RAMs (DRAM) organized as 2M x 16. These devices
feature advanced circuit design to provide ultra-low active current
and extremely low standby current.This is ideal for providing
More Battery Life in portable applications such as wireless
handsets. The device is compatible with the JEDEC standard
LP-SDRAM specifications.
Selection Guide
20ns
20ns
7.5ns
100MHz
18ns
18ns
6ns
133MHz
1.65-VDD
2.3-3.3V
CMS3216LAx-75xx
t
RCD
CL=2
Access Time(t
AC)
CL=3
V
DDQ
V
DD
t
RP
Frequency
Voltage
Device
Column
Decoder
Bank 0
Row
Addr
Latch/
Decoder
Bank 1
Bank 0
Row
Addr
Latch/
Decoder
Bank 0
Memory
Array
2Kx8K
Sense Amp
Row
Add
Mux
Write Drivers
DQM Mask
READ DATA
LATCH
Data
Output
Reg
Column
Address
Latch
Bank
Control
Logic
Refresh
Counter
Addr
Reg
Data
Input
Reg
DQM0-
DQM1
DQ0 -
DQ15
Column
Decoder
Enhanced
Mode
Reg
Mode
Reg
Control
Logic
CKE
CLK
/CS
/WE
/CAS
/RAS
A0-A10
BS
Logic Block Diagram



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