ST72371 datasheet(76/94 Pages) STMICROELECTRONICS

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ST72371/ST72372

8-BIT A/D CONVERTER (ADC)(Cont’d)

4.7.4 Register Description

CONTROL/STATUS REGISTER (CSR)

Read/Write

Reset Value: 0000 0000 (00h)

Bit 7 = COCO Conversion Complete.

This bit is set by hardware. It is cleared by soft-

ware reading the result in the DR register or writing

to the CSR register.

0: Conversion is not complete.

1: Conversion can be read from the DR register.

Bit 6 = Reserved. Must always be cleared.

Bit 5 = ADON A/D converter On.

This bit is set and cleared by software.

0: A/D converter is switched off.

1: A/D converter is switched on.

Note: a typically 30

µs delay time is necessary for

the ADC to stabilize when the ADON bit is set.

Bit 4 = Reserved. Forced by hardware to 0.

Bit 3 = Reserved. Must always be cleared.

Bits 2-0: CH2-CH0 Channel Selection.

These bits are set and cleared by software. They

select the analog input to convert.

Table 21. Channel Selection

(*The number of pins varies according to the de-

vice. Refer to the device pinout).

DATA REGISTER (DR)

Read Only

Reset Value: 0000 0000 (00h)

Bit 7:0 = AD7-AD0 Analog Converted Value.

This register contains the converted analog value

in the range 00h to FFh.

Reading this register reset the COCO flag.

Table 22. ADC Register Map

COCO

ADON

CH2

CH1

CH0

Pin*

CH2

CH1

CH0

AIN0

AIN1

AIN2

AIN3

AIN4

AIN5

AIN6

AIN7

AD7

AD6

AD5

AD4

AD3

AD2

AD1

AD0

Address

(Hex.)

Name

765

3210

CSR

COCO

ADON

CH2

CH1

CH0

AD7 .. AD0

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