ST72371 datasheet(18/94 Pages) STMICROELECTRONICS

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ST72371/ST72372

3.3 INTERRUPTS

The ST7 core may be interrupted by one of two dif-

ferent methods: maskable hardware interrupts as

listed in Table 7 and a non-maskable software in-

terrupt (TRAP). The Interrupt processing flowchart

is shown in Figure 12.

The maskable interrupts must be enabled clearing

the I bit in order to be serviced. However, disabled

interrupts may be latched and processed when

they are enabled (see external interrupts subsec-

tion).

When an interrupt has to be serviced:

– Normal processing is suspended at the end of

the current instruction execution.

– The PC, X, A and CC registers are saved onto

the stack.

– The I bit of the CC register is set to prevent addi-

tional interrupts.

– The PC is then loaded with the interrupt vector of

the interrupt to service and the first instruction of

the interrupt service routine is fetched (refer to

Table 7 for vector addresses).

The interrupt service routine should finish with the

IRET instruction which causes the contents of the

saved registers to be recovered from the stack.

Note: As a consequence of the IRET instruction,

the I bit will be cleared and the main program will

resume.

Priority management

By default, a servicing interrupt can not be inter-

rupted because the I bit is set by hardware enter-

ing in interrupt routine.

In the case several interrupts are simultaneously

pending, an hardware priority defines which one

will be serviced first (see Table 7).

Non Maskable Software Interrupts

This interrupt is entered when the TRAP instruc-

tion is executed regardless of the state of the I bit.

It will be serviced according to the flowchart on

Figure 12.

Interrupts and Low power mode

All interrupts allow the processor to leave the Wait

low power mode. Only external and specific men-

tioned interrupts allow the processor to leave the

Halt low power mode (refer to the “Exit from HALT“

column in Table 7).

External Interrupts

External interrupt vectors can be loaded in the PC

curred and if the I bit is cleared. These interrupts

allow the processor to leave the Halt low power

mode.

The external interrupt polarity can be selected

through the Miscellaneous register or Interrupt

An external interrupt triggered on edge will be

latched and the interrupt request automatically

cleared on entering the interrupt service routine.

More than one input pin can be connected to the

same interrupt request (depending on the device).

In this case, all inputs configured as interrupt are

logically ORed.

Warning: The type of polarity defined in the Mis-

cellaneous or Interrupt register (if available) ap-

plies to the EI source. In case of an ORed source,

a low level on an I/O pin configured as input with

interrupt, masks the interrupt request even in case

of rising-edge polarity.

Peripheral Interrupts

Different peripheral interrupt flags in the status

are active if both:

– The I bit of the CC register is cleared.

– The corresponding enable bit is set in the control

If any of these two conditions is false, the interrupt

is latched and thus remains pending.

Clearing an interrupt request is done by:

– writing “0” to the corresponding bit in the status

– an access to the status register while the flag is

set followed by a read or write of an associated

Note: the clearing sequence resets the internal

latch. A pending interrupt (i.e. waiting for being en-

abled) will therefore be lost if the clear sequence is

executed.

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