LT6554

8

6554fa

Power Supplies

The LT6554 is optimized for ±5V supplies but can be

operated on as little as ±2.25V or a single 4.5V supply and

as much as ±6V or a single 12V supply. Internally, each

supply is independent to improve channel isolation. Do

not leave any supply pins disconnected!

Enable/Shutdown

The LT6554 has a TTL compatible shutdown mode con-

trolled by the EN pin and referenced to the DGND pin. If the

amplifier will be enabled at all times, the EN pin can be

connected directly to DGND. If the enable function is

desired, either driving the pin above 2V or allowing the

internal 46k pull-up resistor to pull the EN pin to the top rail

will disable the amplifier. When disabled, the output will

become very high impedance. Supply current into the

It is important that the two following constraints on the

DGND pin and the EN pin are always followed:

Split supplies of ±3V to ±5.5V will satisfy these require-

ments with DGND connected to 0V.

In single supply applications above 5.5V, an additional

resistor may be needed from the EN pin to DGND if the pin

is ever allowed to float. For example, on a 12V single

supply, a 33k resistor to ground would protect the pin from

floating too high while still allowing the internal pull-up

resistor to disable the part.

On dual ±2.25V supplies, connecting the EN and DGND

is more than 3V.

The DGND pin should not be pulled above the EN pin since

doing so will turn on an ESD protection diode. If the EN pin

voltage is forced a diode drop below the DGND pin, current

should be limited to 10mA or less.

The enable/disable times of the LT6554 are fast when

driven with a logic input. Turn on (from 50% EN input to

50% output) typically occurs in less than 50ns. Turn off is

slower, but is nonetheless below 300ns.

Input Considerations

and is therefore larger than the output swing. The inputs

can be driven beyond the point at which the output clips so

long as input currents are limited to below ±10mA.

Layout and Grounding

It is imperative that care is taken in PCB layout in order to

utilize the very high speed and very low crosstalk of the

LT6554. Separate power and ground planes are highly

recommended and trace lengths should be kept as short

as possible. If input traces must be run over a distance of

several centimeters, they should use a controlled imped-

ance with either series or shunt terminations (nominally

50Ω or 75Ω) to maintain signal fidelity.

Care should be taken to minimize capacitance on the

LT6554’s output traces by increasing spacing between

traces and adjacent metal and by eliminating metal planes

in underlying layers. To drive cable or traces longer than

several centimeters, using the LT6553 with its fixed gain

of +2 in conjunction with series and load termination

resistors may provide better results.

A plot of LT6554 performance driving a 1k load with

various trace lengths is shown in Figure 1. All data is from

a 4-layer board with 2oz copper, 18mil of board layer

thickness to the ground plane, a trace width of 12mils and

spacing to adjacent metal of 18mils. The 0.2cm output

trace places the 1k resistor as close to the part as possible,

while the other curves show the load resistor consecu-

tively further away. The worst case, 4cm, trace has almost

10pF of parasitic capacitance.

In order to counteract any peaking in the frequency re-

sponse from driving a capacitive load, a series resistance

can be inserted in the line at the output of the part to flatten

the response. Figure 2 shows the frequency response with

the same 4cm trace from Figure 1, now with a 10Ω series

resistor inserted near the output pin of the LT6554. Note

that using a 10Ω series resistor with a 1k load only

decreases the output amplitude by 0.1dB or 1% and has a

minimal effect on the bandwidth of the system. See the

graph labeled “Maximum Capacitive Load vs Output Se-

ries Resistor” in the Typical Performance Characteristics

section for more information.

APPLICATIO S I FOR ATIO