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AX2000-1CS896 データシート(PDF) 84 Page - Actel Corporation |
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AX2000-1CS896 データシート(HTML) 84 Page - Actel Corporation |
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84 / 226 page  Axcelerator Family FPGAs 2- 70 v2.7 Adjustable Clock Delay Figure 2-55 illustrates using the PLL to delay the reference clock by employing one of the adjustable delay lines. In this case, the output clock is delayed relative to the reference clock. Delaying the reference clock relative to the output clock is accomplished by using the delay line in the feedback path. Figure 2-55 • Using the PLL Delaying the Reference Clock Delay Line Delay Line PLL RefCLK FB 6 /j 6 CLK1 PowerDown Lock CLK2 FBMuxSel 5 DividerI DelayLine DividerJ LowFreq 3 Osc ÷1 133 MHz 133 MHz /j /i Delay Match /j Delay Match |
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