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LT3478/LT3478-1

34781f

Local heating from the nearby inductor and Schottky diode

will also add to the ﬁnal junction temperature of the IC.

Based on empirical measurements, the effect of diode and

inductor heating on the LT3478-1 junction temperature

can be approximated as:

ΔTJ (LT3478-1) = 5°C/W • (PDIODE + PINDUCTOR)

PDIODE = (1 – D) • VF • IL(AVE)

1 – D = 0.316

VF = 0.5V

IL(AVE) = 2.41

PDIODE = 0.316 • 0.5 • 2.41 = 0.381W

PINDUCTOR = IL(AVE)

2 • DCR

DCR = inductor DC resistance (assume 0.05Ω)

PINDUCTOR = (2.41)

2 • 0.05 = 0.29W

The LT3478/LT3478-1 use a thermally enhanced FE pack-

age. With proper soldering to the Exposed Pad on the

underside of the package combined with a full copper plane

underneath the device, thermal resistance (θJA) will be

about 35°C/W. For an ambient temperature of TA = 70°C,

the junction temperature of the LT3478-1 for the example

application described above, can be calculated as:

TJ (LT3478-1)

= TA + θJA(PTOT) + 5(PDIODE + PINDUCTOR)

= 70 + 35(1.25) + 5(0.671)

= 70 + 44 + 4

= 118°C

In the above example, efﬁciency was initially assumed to

be η = 0.89. A lower efﬁciency (η) for the converter will

increase IL(AVE) and hence increase the calculated value

for TJ. η can be calculated as:

η = POUT/(POUT + PLOSS)

POUT = VOUT • ILED = 17.15W

PLOSS (estimated) = PIC + PDIODE + PINDUCTOR = 1.92W

η = 17.15/(17.15 + 1.92) = 0.9

If an application is built, the inductor current can be mea-

sured and a new value for junction temperature estimated.

Ideally a thermal measurement should be made to achieve

the greatest accuracy for TJ.

Note: The junction temperature of the IC can be reduced

if a lower VIN supply is available – separate from the

inductor supply VS. In the above example, driving VIN

from an available 3V source (instead of VS = 8V) reduces

input quiescent losses in item(4) from 0.597W to 0.224W,

resulting in a reduction of TJ from 118°C to 105°C.

Layout Considerations

As with all switching regulators, careful attention must be

given to PCB layout and component placement to achieve

optimal thermal,electrical and noise performance (Figure

12). The exposed pad of the LT3478/LT3478-1 (Pin 17)

is the only GND connection for the IC. The exposed pad

should be soldered to a continuous copper ground plane

underneath the device to reduce die temperature and

maximize the power capability of the IC. The ground path

for the RT resistor and VC capacitor should be taken from

nearby the analog ground connection to the exposed pad

(near Pin 9) separate from the power ground connection

to the exposed pad (near Pin 16). The bypass capacitor

for VIN should be placed as close as possible to the VIN

pin and the analog ground connection. SW pin voltage rise

and fall times are designed to be as short as possible for

maximum efﬁciency. To reduce the effects of both radiated

and conducted noise, the area of the SW trace should be

kept as small as possible. Use a ground plane under the

switching regulator to minimize interplane coupling. The

schottky diode and output capacitor should be placed as

close as possible to the SW node to minimize this high

frequency switching path. To minimize LED current sensing

errors for the LT3478, the terminals of the external sense

resistor RSENSE should be tracked to the VOUT and LED

pins separate from any high current paths.

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