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CDK8307 データシート(PDF) 6 Page - Cadeka Microcircuits LLC. |
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CDK8307 データシート(HTML) 6 Page - Cadeka Microcircuits LLC. |
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6 / 29 page ![]() ©2009 CADEKA Microcircuits LLC www.cadeka.com 6 PRELIMINARY Data Sheet Pin No. Pin Name Description 51, 54, 55, 56 NC Not connected 53 VCM Common mode output pin, 0.5 AVDD 58 CLKP Positive differential input clock 59 CLKN Negative differential input clock. 60 OVDD Digital CMOS inputs supply voltage (1.7V to 3.6V) 61 CSN Chip select enable. Active low. 62 SDATA Serial data input 63 SCLK Serial clock input 64 RESETN Reset SPI interface QFN-64 (B2 version: AD9222 pinout option) 1, 4, 7, 8, 11, 12, 37, 42, 45, 48, 51, 59, 62 AVDD Analog power supply, 1.8V 0 AVSS Analog ground (Exposed paddle, Pin 0, bottom of package) 60 IP1 Positive differential input signal, channel 1 61 IN1 Negative differential input signal, channel 1 64 IP2 Positive differential input signal, channel 2 63 IN2 Negative differential input signal, channel 2 2 IP3 Positive differential input signal, channel 3 3 IN3 Negative differential input signal, channel 3 6 IP4 Positive differential input signal, channel 4 5 IN4 Negative differential input signal, channel 4 43 IP5 Positive differential input signal, channel 5 44 IN5 Negative differential input signal, channel 5 47 IP6 Positive differential input signal, channel 6 46 IN6 Negative differential input signal, channel 6 49 IP7 Positive differential input signal, channel 7 50 IN7 Negative differential input signal, channel 7 53 IP8 Positive differential input signal, channel 8 52 IN8 Negative differential input signal, channel 8 13, 36 DVSS Digital ground 14, 35 DVDD Digital and I/O power supply, 1.8V 41 PD Power-down input 22 D1P LVDS channel 1, positive output 21 D1N LVDS channel 1, negative output 20 D2P LVDS channel 2, positive output 19 D2N LVDS channel 2, negative output 18 D3P LVDS channel 3, positive output 17 D3N LVDS channel 3, negative output 16 D4P LVDS channel 4, positive output 15 D4N LVDS channel 4, negative output 34 D5P LVDS channel 5, positive output 33 D5N LVDS channel 5, negative output Pin Assignments (Continued) |
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