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LTC2230UP データシート(PDF) 5 Page - Linear Technology

部品番号 LTC2230UP
部品情報  10-Bit,170Msps/135Msps ADCs
PDF  32 Pages
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メーカー  LINER [Linear Technology]
ホームページ  http://www.linear.com
Logo LINER - Linear Technology

LTC2230UP データシート(HTML) 5 Page - Linear Technology

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LTC2230/LTC2231
5
22301fb
POWER REQUIRE E TS
TI I G CHARACTERISTICS The ● denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25
°C. (Note 4)
The
● denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 9)
LTC2230
LTC2231
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
MIN
TYP
MAX
UNITS
VDD
Analog Supply Voltage
(Note 8)
●
3.1
3.3
3.5
3.1
3.3
3.5
V
PSHDN
Shutdown Power
SHDN = H, OE = H, No CLK
2
2
mW
PNAP
Nap Mode Power
SHDN = H, OE = L, No CLK
35
35
mW
LVDS OUTPUT MODE
OVDD
Output Supply Voltage
(Note 8)
●
3
3.3
3.6
3
3.3
3.6
V
IVDD
Analog Supply Current
●
264
288
196
212
mA
IOVDD
Output Supply Current
●
53
68
53
68
mA
PDISS
Power Dissipation
●
1045
1175
822
924
mW
CMOS OUTPUT MODE
OVDD
Output Supply Voltage
(Note 8)
●
0.5
3.3
3.6
0.5
3.3
3.6
V
IVDD
Analog Supply Current
●
264
288
196
212
mA
PDISS
Power Dissipation
890
660
mW
LTC2230
LTC2231
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
MIN
TYP
MAX
UNITS
fS
Sampling Frequency
(Note 8)
●
1
170
1
135
MHz
tL
ENC Low Time (Note 7)
Duty Cycle Stabilizer Off
●
2.8
2.94
500
3.5
3.7
500
ns
Duty Cycle Stabilizer On
●
2
2.94
500
2
3.7
500
ns
tH
ENC High Time (Note 7)
Duty Cycle Stabilizer Off
●
2.8
2.94
500
3.5
3.7
500
ns
Duty Cycle Stabilizer On
●
2
2.94
500
2
3.7
500
ns
tAP
Sample-and-Hold Aperture Delay
0
0
ns
tOE
Output Enable Delay
(Note 7)
●
510
5
10
ns
LVDS OUTPUT MODE
tD
ENC to DATA Delay
(Note 7)
●
1.3
2.2
3.5
1.3
2.2
3.5
ns
tC
ENC to CLOCKOUT Delay
(Note 7)
●
1.3
2.2
3.5
1.3
2.2
3.5
ns
DATA to CLOCKOUT Skew
(tC - tD) (Note 7)
●
–0.6
0
0.6
–0.6
0
0.6
ns
Rise Time
0.5
0.5
ns
Fall Time
0.5
0.5
ns
Pipeline Latency
5
5
Cycles
CMOS OUTPUT MODE
tD
ENC to DATA Delay
(Note 7)
●
1.3
2.1
3.5
1.3
2.1
3.5
ns
tC
ENC to CLOCKOUT Delay
(Note 7)
●
1.3
2.1
3.5
1.3
2.1
3.5
ns
DATA to CLOCKOUT Skew
(tC - tD) (Note 7)
●
–0.6
0
0.6
–0.6
0
0.6
ns
Pipeline Latency Full Rate CMOS
5
5
Cycles
Demuxed Interleaved
5
5
Cycles
Demuxed Simultaneous
5 and 6
5 and 6
Cycles



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