データシートサーチシステム
  Japanese  ▼
ALLDATASHEET.JP

X  

Preview PDF HTML

SPT574BCJ データシート(PDF) 4 Page - Cadeka Microcircuits LLC.

部品番号 SPT574BCJ
部品情報  FAST, COMPLETE 12-BIT mP COMPATIBLE A/D CONVERTER WITH SAMPLE/HOLD
PDF  12 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
メーカー  CADEKA [Cadeka Microcircuits LLC.]
ホームページ  http://www.cadeka.com
Logo CADEKA - Cadeka Microcircuits LLC.

SPT574BCJ データシート(HTML) 4 Page - Cadeka Microcircuits LLC.

  SPT574BCJ Datasheet HTML 1Page - Cadeka Microcircuits LLC. SPT574BCJ Datasheet HTML 2Page - Cadeka Microcircuits LLC. SPT574BCJ Datasheet HTML 3Page - Cadeka Microcircuits LLC. SPT574BCJ Datasheet HTML 4Page - Cadeka Microcircuits LLC. SPT574BCJ Datasheet HTML 5Page - Cadeka Microcircuits LLC. SPT574BCJ Datasheet HTML 6Page - Cadeka Microcircuits LLC. SPT574BCJ Datasheet HTML 7Page - Cadeka Microcircuits LLC. SPT574BCJ Datasheet HTML 8Page - Cadeka Microcircuits LLC. SPT574BCJ Datasheet HTML 9Page - Cadeka Microcircuits LLC. Next Button
Zoom Inzoom in Zoom Outzoom out
 4 / 12 page
background image
SPT574
ELECTRICAL SPECIFICATIONS
TA = TMIN to TMAX, VEE = 0 to +5 V, VDD = +5 V, fS = 40 kHz, fIN = 10 kHz, unless otherwise specified.
TEST
TEST
SPT574C
SPT574B
PARAMETER
CONDITIONS
LEVEL
MIN
TYP
MAX
MIN
TYP
MAX
UNITS
AC ELECTRICAL CHARACTERISTICS4
Convert Mode Timing
tDSC STS Delay from CE
VI
60
200
60
200
ns
tHEC CE Pulse Width
VI
50
30
50
30
ns
tSSC CS to CE Setup
VI
50
20
50
20
ns
tHSC CS Low during CE High
VI
50
20
50
20
ns
tSRC R/C to CE Setup
VI
50
0
50
0
ns
tHRC R/C Low During CE High
VI
50
20
50
20
ns
tSAC Ao to CE Setup
VI
0
0
ns
tHAC Ao Valid During CE High
VI
50
20
50
20
ns
tC Conversion Time5
12-Bit Cycle
VI
22
25
22
25
µs
8-Bit Cycle
VI
16
18
16
18
µs
Read Mode Timing
tDD Access Time from CE
VI
75
150
75
150
ns
tHD Data Valid After CE Low
VI
25
35
25
35
ns
tHL Output Float Delay
VI
100
150
100
150
ns
tSSR CS to CE Setup
VI
50
0
50
0
ns
tSRR R/C to CE Setup
VI
0
0
ns
tSAR Ao to CE Setup
VI
50
25
50
25
ns
tHSR CS Valid After CE Low
VI
0
0
ns
tHRR R/C High After CE Low
VI
0
0
ns
tHS STS Delay After Data Valid
VI
300
400
1000
300
400
1000
ns
tHAR Ao Valid after CE Low
VI
50
50
ns
Note 4: Time is measured from 50% level of digital transitions.
Note 5: Includes acquisition time.
tHEC
t
SSC
t SRC
t HSC
t HRC
t
HAC
t SAC
t DSC
High Impedance
tC
DB11-DB0
STS
Ao
R/C
CE
CS
Figure 1 - Convert Mode Timing Diagram
Figure 2 - Read Mode Timing Diagram
t SSR
Ao
CE
CS
t HSR
t HRR
t SRR
t SAR
t HAR
STS
DATA
VALID
t HL
HIGH
IMPEDANCE
DB11-DB0
R/C
t HS
t HD
t DD
4
8/1/00



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12


データシート ダウンロード

Go To PDF Page


リンク URL



ALLDATASHEETはお客様のビジネスに役立ちますか？  [ DONATE ] 

Alldatasheetは   |   広告   |   お問い合わせ   |   プライバシーポリシー   |   データシートへのリンク    |   リンク交換   |   メーカーリスト
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com