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MCP3202 データシート(PDF) 3 Page - Microchip Technology

部品番号 MCP3202
部品情報  2.7V Dual Channel 12-Bit A/D Converter with SPI Serial Interface
PDF  32 Pages
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メーカー  MICROCHIP [Microchip Technology]
ホームページ  http://www.microchip.com
Logo MICROCHIP - Microchip Technology

MCP3202 データシート(HTML) 3 Page - Microchip Technology

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© 2008 Microchip Technology Inc.
DS21034E-page 3
MCP3202
1.0
ELECTRICAL
CHARACTERISTICS
Absolute Maximum Ratings †
VDD –VSS ........................................................................7.0V
All Inputs and Outputs w.r.t. VSS ............– 0.6V to VDD +0.6V
Storage Temperature ................................... –65°C to +150°C
Ambient temperature with power applied.......–65°C to +150°C
Maximum Junction Temperature (TJ)......................... .+150°C
ESD Protection On All Pins (HBM)
...................................≥ 4kV
† Notice:
Stresses above those listed under “Absolute
Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of
the device at those or any other conditions above those
indicated in the operational listings of this specification is not
implied. Exposure to maximum rating conditions for extended
periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
Electrical Characteristics:
Unless otherwise noted, all parameters apply at VDD = 5.5V, VSS = 0V,
TA = -40°C to +85°C, fSAMPLE = 100 ksps and fCLK = 18*fSAMPLE.
Parameter
Sym
Min.
Typ.
Max.
Units
Conditions
Conversion Rate:
Conversion Time
tCONV
12
clock
cycles
Analog Input Sample Time
tSAMPLE
1.5
clock
cycles
Throughput Rate
fSAMPL
100
50
ksps
ksps
VDD = VREF = 5V
VDD = VREF = 2.7V
DC Accuracy:
Resolution
12
bits
Integral Nonlinearity
INL
±0.75
±1
±1
±2
LSB
LSB
MCP3202-B
MCP3202-C
Differential Nonlinearity
DNL
±0.5
±1
LSB
No missing codes over
temperature
Offset Error
±1.25
±3
LSB
Gain Error
±1.25
±5
LSB
Dynamic Performance:
Total Harmonic Distortion
THD
-82
dB
VIN = 0.1V to 4.9V@1 kHz
Signal-to-Noise and Distortion
(SINAD)
SINAD
72
dB
VIN = 0.1V to 4.9V@1 kHz
Spurious Free Dynamic Range
SFDR
86
dB
VIN = 0.1V to 4.9V@1 kHz
Analog Inputs:
Input Voltage Range for CH0 or
CH1 in Single-Ended Mode
VSS
—VDD
V
Input Voltage Range for IN+ in
Pseudo-Differential Mode
IN+
IN-
VDD+IN-
See Sections 3.1 and 4.1
Input Voltage Range for IN- in
Pseudo-Differential Mode
IN-
VSS-100
VSS+100
mV
See Sections 3.1 and 4.1
Leakage Current
.001
±1
μA
Switch Resistance
RSS
—1 k
See Figure 4-1
Sample Capacitor
CSAMPLE
20
pF
See Figure 4-1
Digital Input/Output:
Data Coding Format
Straight Binary
High Level Input Voltage
VIH
0.7 VDD
——
V
Low Level Input Voltage
VIL
0.3 VDD
V
Note 1:
This parameter is established by characterization and not 100% tested.
2:
Because the sample cap will eventually lose charge, effective clock rates below 10 kHz can affect linearity performance,
especially at elevated temperatures. See Section 6.2 “Maintaining Minimum Clock Speed” for more information.



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