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MCP3202 データシート(PDF) 17 Page - Microchip Technology

部品番号 MCP3202
部品情報  2.7V Dual Channel 12-Bit A/D Converter with SPI Serial Interface
PDF  32 Pages
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メーカー  MICROCHIP [Microchip Technology]
ホームページ  http://www.microchip.com
Logo MICROCHIP - Microchip Technology

MCP3202 データシート(HTML) 17 Page - Microchip Technology

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© 2008 Microchip Technology Inc.
DS21034E-page 17
MCP3202
5.0
SERIAL COMMUNICATIONS
5.1
Overview
Communication with the MCP3202 is done using a
standard SPI-compatible serial interface. Initiating
communication with the device is done by bringing the
CS line low. See Figure 5-1. If the device was powered
up with the CS pin low, it must be brought high and
back low to initiate communication. The first clock
received with CS low and DIN high will constitute a start
bit. The SGL/DIFF bit and the ODD/SIGN bit follow the
start bit and are used to select the input channel
configuration. The SGL/DIFF is used to select single
ended or psuedo-differential mode. The ODD/SIGN bit
selects which channel is used in single ended mode,
and is used to determine polarity in pseudo-differential
mode. Following the ODD/SIGN bit, the MSBF bit is
transmitted to and is used to enable the LSB first format
for the device. If the MSBF bit is high, then the data will
come from the device in MSB first format and any
further clocks with CS low will cause the device to
output zeros. If the MSBF bit is low, then the device will
output the converted word LSB first after the word
has been transmitted in the MSB first format.
See Figure 5-2. Table 5-1 shows the configuration bits
for the MCP3202. The device will begin to sample the
analog input on the second rising edge of the clock,
after the start bit has been received. The sample period
will end on the falling edge of the third clock following
the start bit.
On the falling edge of the clock for the MSBF bit, the
device will output a low null bit. The next sequential
12 clocks will output the result of the conversion with
MSB first as shown in Figure 5-1. Data is always output
from the device on the falling edge of the clock. If all
12 data bits have been transmitted and the device
continues to receive clocks while the CS is held low,
(and MSBF = 1), the device will output the conversion
result LSB first as shown in Figure 5-2. If more clocks
are provided to the device while CS is still low (after the
LSB first data has been transmitted), the device will
clock out zeros indefinitely.
If necessary, it is possible to bring CS low and clock in
leading zeros on the DIN line before the start bit. This is
often done when dealing with microcontroller-based
SPI ports that must send 8 bits at a time. Refer to
Section 6.1 “Using the MCP3202 with Microcon-
troller (MCU) SPI Ports”
for more details on using the
MCP3202 devices with hardware SPI ports.
FIGURE 5-1:
Communication with the MCP3202 using MSB first format only.
TABLE 5-1:
CONFIGURATION BITS FOR
THE MCP3202
Config
Bits
Channel
Selection
GND
SGL/
DIFF
ODD/
SIGN
01
Single Ended
Mode
10
+
-
11
+
-
Pseudo-
Differential
Mode
00
IN+
IN-
01
IN-
IN+
CS
CLK
DIN
DOUT
MS
HI-Z
Null
Bit B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0*
HI-Z
tSAMPLE
tCONV
SGL/
DIFF
Start
tCYC
tCSH
tCYC
* After completing the data transfer, if further clocks are applied with CS low, the A/D Converter will output zeros
indefinitely. See Figure 5-2 below for details on obtaining LSB first data.
** tDATA: during this time, the bias current and the comparator power down while the reference input becomes a
high-impedance node, leaving the CLK running to clock out the LSB-first data or zeros.
tDATA**
tSUCS
ODD/
SIGN BF
Don’t Care
SGL/
DIFF
Start
ODD/
SIGN



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