FM24V10 - 1Mb I2C FRAM

Rev. 1.1

Feb. 2009

Page 13 of 15

AC Test Conditions

Equivalent AC Test Load Circuit

Input Pulse Levels

Input rise and fall times

10 ns

Input and output timing levels

Diagram Notes

All start and stop timing parameters apply to both read and write cycles.

Clock specifications are identical for read and write cycles. Write timing

parameters apply to slave address, word address, and write data bits.

Functional relationships are illustrated in the relevant datasheet sections.

These diagrams illustrate the timing parameters only.

Read Bus Timing

t

SU:SDA

Start

t

R

`

t

F

Stop Start

t

BUF

t

HIGH

1/fSCL

t

LOW

t

SP

t

SP

Acknowledge

t

HD:DAT

t

SU:DAT

t

AA

t

DH

SCL

SDA

Write Bus Timing

t

SU:STO

Start

Stop Start

Acknowledge

t

AA

t

HD:DAT

t

HD:STA

t

SU:DAT

SCL

SDA

Power Cycle Timing

Parameter

Min

Max

Units

Notes

Data Retention

10

-

Years

3.6V

Output

100 pF