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CPC7591MATR データシート(PDF) 12 Page - Clare, Inc.

部品番号 CPC7591MATR
部品情報  Line Card Access Switch
PDF  19 Pages
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メーカー  CLARE [Clare, Inc.]
ホームページ  http://www.clare.com
Logo CLARE - Clare, Inc.

CPC7591MATR データシート(HTML) 12 Page - Clare, Inc.

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R05
Make-Before-Break Ringing to Talk Transition Logic Sequence
2.3.4 Break-Before-Make Operation
Break-before-make ringing switch release timing is
performed via the bidirectional TSD interface. As an
input, the TSD can disable all of the CPC7591 switches
when pulled to a logic low. Although logically disabled,
an active (closed) ringing switch (SW4) will remain
closed until the next current zero crossing event. This
operational sequence is shown below in the
“Break-Before-Make Ringing to Talk Transition Logic
Sequence” on page 12.
1.
Pull TSD to a logic low to end the ringing state.
This opens the ringing return switch (SW3) and
prevents any other switches from closing.
2.
Keep TSD low for at least one-half the duration of
the ringing cycle period to allow sufficient time for
a zero crossing current event to occur and for the
circuit to enter the break before make state.
3.
During the TSD low period, clear the INRINGING
input for the talk state (logic low).
4.
Release TSD allowing the internal pull-up to
activate the break switches.
When using TSD as an input, the two recommended
states are “0” which overrides the logic input pins and
forces an all-off state and “Z” which allows normal
switch control via the logic input pins. This requires the
use of an open-collector or open-drain type buffer.
Break-Before-Make Ringing to Talk Transition Logic Sequence
Logic states and explanations are provided in the “Truth Table” on page 9.
2.4 Data Latch
The CPC7591 has an integrated transparent data
latch. The latch enable operation is controlled by TTL
logic input levels at the LATCH pin. Data input to the
latch is via the input pin INRINGING, while the output of
the data latch are internal nodes used for state control.
When the LATCH enable control pin is at logic 0 the
data latch is transparent and the INRINGING input data
control signal flows directly through the data latch to
the state control circuitry. A change in INRINGING input
will be reflected by a change in switch state.
State
INRINGING
Latch
TSD
Timing
Break
Switches
Ringing
Return
Switch
(SW3)
Ringing
Switch
(SW4)
Ringing
1
0Z
-Off
On
On
Make-
Before-
Break
0
SW4 waiting for next zero-current crossing to
turn off. Maximum time is one-half of the ringing
cycle. In this transition state, current that is
limited to the dc break switch current limit value
will be sourced from the ring node of the SLIC.
On
Off
On
Talk
0
Zero-cross current has occurred
On
Off
Off
State
INRINGING
Latch
TSD
Timing
Break
Switches
Ringing
Return
Switch
(SW3)
Ringing
Switch
(SW4)
Ringing
1
0
Z-
Off
On
On
All-off
1
0
Hold this state for one-half of the ringing cycle.
SW4 waiting for zero current to turn off.
Off
Off
On
All-off
0
Zero current has occurred. SW4 has opened
Off
Off
Off
Talk
0
Z
Close break switches
On
Off
Off



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