MAXQ3181-RAN+ datasheet(75/84 Pages) MAXIM

75 / 84 page

Low-Power, Active Energy, Polyphase AFE

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Timeouts

Zero-Crossing Timeout (NZX_TIMO) (0x054)

This register specifies the time in ADC sample periods (default 40μs) that must elapse following a zero-crossing

event before the MAXQ3181 declares a “no-zero crossing” fault. When this fault is declared, the NOZXF bit in the

X.FLAGS register is set.

Communications Timeout (COM_TIMO) (0x056)

This register specifies the duration of SPI timeout in ADC frames (default 320μs).

Energy Accumulation Timeout (ACC_TIMO) (0x058)

This register specifies the time in DSP cycles that the MAXQ3181 waits before accumulating energy. If this register is

nonzero, it is decremented on each DSP cycle. If the result of the decrement is nonzero, the results of the DSP cycle

are discarded and are not accumulated to the energy registers. This register is useful for delaying the initiation of

energy accumulation on startup or after some hardware function has been modified.

Bit:

Name:

Zero-Crossing Timeout High Byte

Reset:

0x23

Bit:

Name:

Zero-Crossing Timeout Low Byte

Reset:

0x28

Bit:

Name:

Communications Timeout High Byte

Reset:

0x03

Bit:

Name:

Communications Timeout Low Byte

Reset:

0xE8

Bit:

Name:

Energy Accumulation Timeout High Byte

Reset:

0x00

Bit:

Name:

Energy Accumulation Timeout Low Byte

Reset:

0x05

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