AD9393SLASHPCBZ datasheet(22/40 Pages) AD

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AD9393

Rev. 0 | Page 22 of 40

2-WIRE SERIAL CONTROL REGISTER DETAILS

This section describes certain register details. Note that not all

registers are discussed in this section.

CHIP IDENTIFICATION

0x00—Bits[7:0], Chip Revision

An 8-bit value that reflects the current chip revision.

0x17—Bits[3:0], HSYNCs per VSYNC MSB

These bits are four MSBs of the 12-bit counter that reports the

number of HSYNCs per VSYNC on the active input. This is

useful in determining the mode and aid in setting the PLL

divide ratio.

0x18—Bit[7:0], HSYNCs per VSYNC LSB

These bits are eight LSBs of the 12-bit counter that reports the

number of HSYNCs per VSYNCs on the active input.

0x23—Bits[7:0], HSYNC Duration

These bits are an 8-bit register that sets the duration of the

HSYNC output pulse. The leading edge of the HSYNC output

is triggered by the internally generated, phase-adjusted PLL

feedback clock. The AD9393 then counts a number of pixel

clocks equal to the value in this register. This triggers the

trailing edge of the HSYNC output, which is also phase-

adjusted. The power-up default is 32.

0x24—Bit[7], HSYNC Output Polarity

This bit sets the polarity of the HSYNC output. Setting this bit

to 0 sets the HSYNC output to active low. Setting this bit to 1

sets the HSYNC output to active high. The power-up default

setting is 1.

0x24—Bit[6], VSYNC Output Polarity

This bit sets the polarity of the VSYNC output. Setting this bit to 0

sets the VSYNC output to active low. Setting this bit to 1 sets the

VSYNC output to active high. The power-up default is 1.

0x24—Bit[5] DE Output Polarity

This bit sets the polarity of the display enable (DE). 0 = DE

output polarity is negative. 1 = DE output polarity is positive.

The power-up default is 1.

0x24—Bit[4], Field Output Polarity

This bit sets the polarity of the odd/even field output signal on

Ball A7. 0 = active low = even field; active high = odd field. 1 =

active high = odd field; active high = even field. The power-up

default setting is 1.

0x24—Bit[0], Output CLK Invert

This bit allows inversion of the output clock as specified by

clock. The power-up default setting is 0.

0x25—Bits[7:6], Output CLK Select

These bits select the clock output on the DCLK ball. They

include ½× clock, a 2× clock, a 90° phase shifted clock, or

the normal pixel clock. The power-up default setting is 01.

See Table 10.

Table 10. Output Clock Select

Select

Result

½× pixel clock

1× pixel clock

2× pixel clock

90° phase 1× pixel clock

0x25—Bits[5:4], Output Drive Strength

These two bits select the drive strength for all the high speed

digital outputs (except the VSOUT, HSOUT, and O/E). Higher

drive strength results in faster rise/fall times and in general

makes it easier to capture data. Lower drive strength results in

slower rise/fall times and helps to reduce EMI and digitally

generated power supply noise. The power-up default setting is

11. See Table 11.

Table 11. Output Drive Strength

Output Drive

Result

Low output drive strength

Medium low output drive strength

Medium high output drive strength

High output drive strength

0x25—Bits[3:2], Output Mode

These bits choose between four options for the output mode.

4:4:4 mode is standard RGB; 4:2:2 mode is YCrCb, which

reduces the number of active output pins from 24 to 16; 4:4:4

is double data rate (DDR) output mode; and the data is RGB

mode that changes on every clock edge. The power-up default

setting is 00. See Table 12.

Table 12. Output Mode

Output

Mode

Result

4:4:4 RGB mode

4:2:2 YCrCb mode + DDR 4:2:2 on D[7:0] (secondary)

DDR 4:4:4 DDR mode + DDR 4:2:2 on D[7:0] (secondary)

12-bit 4:2:2

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