ADL5358

Rev. 0 | Page 6 of

24

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

24

25

26

23

22

21

1

2

3

9

20

27

19

4

5

6

7

8

VGS0

VGS1

VGS2

LOSW

PWDN

VPOS

COMM

LOI2

LOI1

MNIN

MNCT

COMM

DVIN

VPOS

COMM

VPOS

COMM

DVCT

ADL5358

TOP VIEW

(Not to Scale)

NOTES

1. NC = NO CONNECT.

2. EXPOSED PAD MUST BE CONNECTED TO GROUND.

Figure 2. Pin Configuration

Table 6. Pin Function Descriptions

Pin No.

Mnemonic

Description

1

MNIN

RF Input for Main Channel. Internally matched to 50 Ω. This pin must be ac-coupled.

2

MNCT

Center Tap for Main Channel Input Balun. Bypass this pin to ground using low inductance capacitor.

3, 5, 7, 12, 20, 34

COMM

Device Common (DC Ground).

4, 6, 10, 16,

21, 30, 36

VPOS

Positive Supply Voltage.

8

DVCT

Center Tap for Diversity Channel Input Balun. Bypass to ground using low inductance capacitor.

9

DVIN

RF Input for Diversity Channel. Internally matched to 50 Ω. This pin must be ac-coupled.

11

DVGM

Diverstiy Amplifier Bias Setting. Connect a 1.3 kΩ resistor to ground for typical operation.

13, 14

DVOP, DVON

Diversity Channel Differential Open-Collector Outputs. DVOP and DVON should be pulled-up to

VCC using external inductors.

15

DVLE

Diversity Channel IF Return. This pin must be grounded.

17

DVLG

Diverstiy Channel LO Buffer Bias Setting. Connect a 1 kΩ resistor to ground for typical operation.

18, 28

NC

No Connect.

19

LOI1

Local Oscillator Input 1. Internally matched to 50 Ω. This pin must be ac-coupled.

22

PWDN

Connect to Ground for Normal Operation. Connect this pin to 3 V for disable mode when using

VPOS < 3.6 V. PWDN pin must be grounded when VPOS > 3.6 V.

23

LOSW

Local Oscillator Input Selection Switch. Set LOSW high to select LOI1 or set LOSW low to select LOI2.

24, 25, 26

VGS0, VGS1, VGS2

Gate to Source Control Voltages. For typical operation, set VGS0, VGS1, and VGS2 to low logic level.

27

LOI2

Local Oscillator Input 2. Internally matched to 50 Ω. This pin must be ac-coupled.

29

MNLG

Main Channel LO Buffer Bias Setting. Connect a 1 kΩ resistor to ground for typical operation.

31

MNLE

Main Channel IF Return. This pin must be grounded.

32, 33

MNOP, MNON

Main Channel Differential Open-Collector Outputs. MNOP and MNON should be pulled-up to

VCC using external inductors.

35

MNGM

Main Amplifier Bias Setting. Connect a 1.3 kΩ resistor to ground for typical operation.

Paddle

EPAD

Exposed pad must be connected to ground.