MCP6401RT-E datasheet(14/28 Pages) MICROCHIP

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MCP6401/1R/1U

DS22229A-page 14

4.3

Capacitive Loads

Driving large capacitive loads can cause stability

problems for voltage feedback op amps. As the load

capacitance increases, the feedback loop’s phase

margin decreases and the closed-loop bandwidth is

reduced. This produces gain peaking in the frequency

response, with overshoot and ringing in the step

response. While a unity-gain buffer (G = +1 V/V) is the

most sensitive to capacitive loads, all gains show the

same general behavior.

When driving large capacitive loads with these op

amps (e.g., > 100 pF when G = +1 V/V), a small series

resistor at the output (RISO in Figure 4-3) improves the

feedback loop’s phase margin (stability) by making the

output load resistive at higher frequencies. The

bandwidth will be generally lower than the bandwidth

with no capacitance load.

FIGURE 4-3:

Output Resistor, RISO

Stabilizes Large Capacitive Loads.

Figure 4-4 gives recommended RISO values for

different capacitive loads and gains. The x-axis is the

normalized load capacitance (CL/GN), where GN is the

circuit's noise gain. For non-inverting gains, GN and the

Signal Gain are equal. For inverting gains, GN is

1+|Signal Gain| (e.g., -1 V/V gives GN = +2 V/V).

FIGURE 4-4:

Recommended RISO Values

for Capacitive Loads.

After selecting RISO for your circuit, double-check the

resulting

frequency

response

peaking

and

step

response overshoot. Modify RISO’s value until the

response

reasonable.

Bench

evaluation

and

simulations with the MCP6401/1R/1U SPICE macro

model are very helpful.

4.4

Supply Bypass

With this family of operational amplifiers, the power

supply pin (VDD for single-supply) should have a local

bypass capacitor (i.e., 0.01 µF to 0.1 µF) within 2 mm

for good high frequency performance. It can use a bulk

capacitor (i.e., 1 µF or larger) within 100 mm to provide

large, slow currents. This bulk capacitor can be shared

with other analog parts.

4.5

PCB Surface Leakage

In applications where low input bias current is critical,

Printed Circuit Board (PCB) surface leakage effects

need to be considered. Surface leakage is caused by

humidity, dust or other contamination on the board.

Under low humidity conditions, a typical resistance

between nearby traces is 1012

Ω. A 5V difference would

cause 5 pA of current to flow; which is greater than the

MCP6401/1R/1U family’s bias current at +25°C

(±1.0 pA, typical).

The easiest way to reduce surface leakage is to use a

guard ring around sensitive pins (or traces). The guard

ring is biased at the same voltage as the sensitive pin.

An example of this type of layout is shown in

Figure 4-5.

FIGURE 4-5:

Example Guard Ring Layout

for Inverting Gain.

Non-inverting Gain and Unity-Gain Buffer:

Connect the non-inverting pin (VIN+) to the

input with a wire that does not touch the

PCB surface.

Connect the guard ring to the inverting input

pin (VIN–). This biases the guard ring to the

common mode input voltage.

Inverting

Gain

and

Transimpedance

Gain

Amplifiers (convert current to voltage, such as

photo detectors):

Connect the guard ring to the non-inverting

input pin (VIN+). This biases the guard ring

to the same reference voltage as the op

amp (e.g., VDD/2 or ground).

Connect the inverting pin (VIN–) to the input

with a wire that does not touch the PCB

surface.

VIN

RISO

VOUT

–

MCP640x

100

1000

10000

1.E-11

1.E-10

1.E-09

1.E-08

1.E-07

1.E-06

Normalized Load Capacitance; CL/GN (F)

GN:

1 V/V

2 V/V

≥ 5 V/V

VDD = 6.0 V

RL = 10 kΩ

10p

100p

10n

0.1µ

1µ

Guard Ring

VIN–VIN+

VSS

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