データシートサーチシステム
  Japanese  ▼
ALLDATASHEET.JP

X  

PCF2129AT データシート(PDF) 29 Page - NXP Semiconductors

部品番号 PCF2129AT
部品情報  Integrated RTC, TCXO and quartz crystal
PDF  68 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
メーカー  NXP [NXP Semiconductors]
ホームページ  http://www.nxp.com
Logo NXP - NXP Semiconductors

PCF2129AT データシート(HTML) 29 Page - NXP Semiconductors

Back Button PCF2129AT Datasheet HTML 25Page - NXP Semiconductors PCF2129AT Datasheet HTML 26Page - NXP Semiconductors PCF2129AT Datasheet HTML 27Page - NXP Semiconductors PCF2129AT Datasheet HTML 28Page - NXP Semiconductors PCF2129AT Datasheet HTML 29Page - NXP Semiconductors PCF2129AT Datasheet HTML 30Page - NXP Semiconductors PCF2129AT Datasheet HTML 31Page - NXP Semiconductors PCF2129AT Datasheet HTML 32Page - NXP Semiconductors PCF2129AT Datasheet HTML 33Page - NXP Semiconductors Next Button
Zoom Inzoom in Zoom Outzoom out
 29 / 68 page
background image
PCF2129A_1
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 01 — 13 January 2010
29 of 68
NXP Semiconductors
PCF2129A
Integrated RTC, TCXO and quartz crystal
8.10 Timer functions
The PCF2129A has a watchdog timer function. The timer can be selected by using the
control bit WD_CD in the register Watchdg_tim_ctl.
The watchdog timer has four selectable source clocks. It can be used to detect a
microprocessor with interrupt and reset capability which is out of control (see
Section 8.10.3)
To control the timer function and timer output, the registers Control_2, Watchdg_tim_ctl,
and Watchdg_tim_val are used.
8.10.1 Register Watchdg_tim_ctl
[1]
Default value.
[2]
When writing to the register this bit has always to be set logic 0.
8.10.2 Register Watchdg_tim_val
Table 30.
Watchdg_tim_ctl - watchdog timer control register (address 10h) bit description
Bit
Symbol
Value
Description
7
WD_CD
0[1]
watchdog timer disabled
1
watchdog timer enabled;
the interrupt pin INT is activated when timed out
6T
0[2]
unused
5TI_TP
0[1]
the interrupt pin INT is configured to generate a
permanent active signal when MSF (register Control_2)
is set
1
the interrupt pin INT is configured to generate a pulsed
signal when MSF flag is set (see Figure 19)
4to2
-
unused
1 to 0 TF[1:0]
timer source clock for watchdog timer
00
4.096 kHz
01
64 Hz
10
1 Hz
11[1]
1
60 Hz
Table 31.
Watchdg_tim_val - watchdog timer value register (address 11h) bit description
Bit
Symbol
Value
Description
7 to 0 WATCHDG_TIM_VAL[7:0]
00 to FF
countdown period in seconds:
where n is the countdown value
CountdownPeriod
n
SourceClockFrequency
---------------------------------------------------------------
=



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68


データシート ダウンロード

Go To PDF Page


リンク URL



ALLDATASHEETはお客様のビジネスに役立ちますか?  [ DONATE ] 

Alldatasheetは   |   広告   |   お問い合わせ   |   プライバシーポリシー   |   データシートへのリンク    |   リンク交換   |   メーカーリスト
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com