PCF2129AT datasheet(47/68 Pages) NXP

47 / 68 page

PCF2129A_1

Product data sheet

Rev. 01 — 13 January 2010

47 of 68

NXP Semiconductors

PCF2129A

Integrated RTC, TCXO and quartz crystal

9.2 I2C-bus interface

The I2C-bus is for bidirectional, two-line communication between different ICs or modules.

The two lines are a Serial DAta line (SDA) and a Serial Clock Line (SCL). Both lines are

connected to a positive supply via a pull-up resistor. Data transfer is initiated only when

the bus is not busy.

9.2.1 Bit transfer

One data bit is transferred during each clock pulse. The data on the SDA line remains

stable during the HIGH period of the clock pulse as changes in the data line at this time

are interpreted as control signals (see Figure 31).

9.2.2 START and STOP conditions

Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW

transition of the data line, while the clock is HIGH, is defined as the START condition S. A

LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the STOP

condition P (see Figure 32).

For this device a repeated START is not allowed for reading. Therefore a STOP has to be

released before the next START.

9.2.3 System configuration

A device generating a message is a transmitter; a device receiving a message is the

receiver. The device that controls the message is the master; and the devices which are

controlled by the master are the slaves.

The PCF2129A can act as a slave transmitter and a slave receiver.

Fig 31. Bit transfer

mbc621

data line

stable;

data valid

change

of data

allowed

SDA

SCL

Fig 32. Definition of START and STOP conditions

mbc622

SDA

SCL

STOP condition

SDA

SCL

START condition

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