10-16GHz Low Noise Amplifier

CHA2066

Ref. : DSCHA20661257 -14-Sept-01

7/8

Specifications subject to change without notice

Route Départementale 128 , B.P.46 - 91401 ORSAY Cedex - FRANCE

Tel.: +33 (0)1 69 33 03 08 - Fax : +33 (0)1 69 33 03 09

Typical Chip Assembly

B

E

Vd

IN

C = 100pF

OUT

Chip Biasing options

This chip is self-biased, and flexibility is provided by the access to number of pads. the

internal DC electrical schematic is given in order to use these pads in a safe way.

The two requirements are :

N°1 : Not exceed Vds = 3.5Volt

( internal Drain to Source voltage ).

N°2 : Not biased in such a way that Vgs becomes positive.

( internal Gate to Source voltage )

We propose two standard biasing :

Low Noise and low consumption :

Vd = 4V and B & D grounded.

All the other pads non connected ( NC ).

Idd = 45mA & Pout-1dB = +10dBm Typical.

( Equivalent to A,B,C,D,E : NC and Vd=4V ; G1=+1.4V ; G2=+1.4V).

Low Noise and high output power :

Vd = 4V and B & E grounded.

All the other pads non connected ( NC ).

Idd = 55mA & Pout-1dB = +13dBm Typical.

( Equivalent to A,B,C,D,E : NC and Vd=5V ; G1=+1.4V ; G2=+4.0V).

A file is available on request to help the biasing option tuning.