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CS49310 データシート(PDF) 18 Page - Cirrus Logic

部品番号 CS49310
部品情報  Multi-Standard Audio Decoder Family
PDF  90 Pages
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メーカー  CIRRUS [Cirrus Logic]
ホームページ  http://www.cirrus.com
Logo CIRRUS - Cirrus Logic

CS49310 データシート(HTML) 18 Page - Cirrus Logic

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CS49300 Family DSP
18
DS339F7
1.12. Switching Characteristics — Digital Audio Input
(VA, VD[3:1] = 2.5 V
±5%; Inputs: Logic 0 = DGND, Logic 1 = VD, CL = 20 pF)
Notes: 1. Master mode timing specifications are characterized, not production tested.
2. Master mode is defined as the CS493XX driving LRCLKN1(2) and SCLKN1(2). Master or Slave mode
can be programmed.
3. This timing parameter is defined from the non-active edge of SCLKN1(2). The active edge of
SCLKN1(2) is the point at which the data is valid.
4. This timing parameter is defined from the active edge of SCLKN1(2). The active edge of SCLKN1(2) is
the point at which the data is valid.
5. Slave mode is defined as SCLKN1(2) and LRCLKN1(2) being driven by an external source.
Parameter
Symbol
Min
Max
Unit
SCLKN1(2) period for both Master and Slave mode
(Note 1)
Tsclki
40
-
ns
SCLKN1(2) duty cycle for Master and Slave mode
(Note 1)
45
55
%
Master Mode
(Note 1, 2)
LRCLKN1(2) delay after SCLKN1(2) transition
(Note 3)
Tlrds
-10
ns
SDATAN1(2) setup to SCLKN1(2) transition
(Note 4)
Tsdsum
10
-
ns
SDATAN1(2) hold time after SCLKN1(2) transition
(Note 4)
Tsdhm
5-
ns
Slave Mode
(Note 5)
Time from active edge of SCLKN1(2) to LRCLKN1(2) transition
Tstlr
10
-
ns
Time from LRCLKN1(2) transition to SCLKN1(2) active edge
Tlrts
10
-
ns
SDATAN1(2) setup to SCLKN1(2) transition
(Note 4)
Tsdsus
5-
ns
SDATAN1(2) hold time after SCLKN1(2) transition
(Note 4)
Tsdhs
5-
ns



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