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CS49326 データシート(PDF) 79 Page - Cirrus Logic |
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CS49326 データシート(HTML) 79 Page - Cirrus Logic |
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79 / 90 page  CS49300 Family DSP DS339F7 79 22 Multichannel (2 channel) 20-bit Left Justified (SCLK must be at least 128Fs for this mode) (Configuration of AUDATA3 as S/PDIF (IEC60958) or Digital Audio in the format of I2S or Left Justified is covered in AN162 and AN163) 0x80027F 0xFC7FFF 0x80017F 0x018000 0x80027C 0xF01F00 0x80017C 0x001300 24 Multichannel (4 channel) 20-bit Left Justified (SCLK must be at least 128Fs for this mode) (Configuration of AUDATA3 as S/PDIF (IEC60958) or Digital Audio in the format of I2S or Left Justified is covered in AN162 and AN163) 0x80027F 0xFC7FFF 0x80017F 0x010000 0x80027C 0xF01F00 0x80017C 0x001300 3 Multichannel (6 channel) 24-bit Left Justified (SCLK must be at least 256Fs for this mode) (Configuration of AUDATA3 as S/PDIF (IEC60958) or Digital Audio in the format of I2S or Left Justified is covered in AN162 and AN163) 0x80027F 0xFC7FFF 0x80027C 0xF01F00 0x80027D 0xF01F00 0x80027E 0xF01F00 32 Multichannel (2 channel) 24-bit Left Justified (SCLK must be at least 128Fs for this mode) (Configuration of AUDATA3 as S/PDIF (IEC60958) or Digital Audio in the format of I2S or Left Justified is covered in AN162 and AN163) 0x80027F 0xFC7FFF 0x80027C 0xF01F00 0x80017F 0x018000 34 Multichannel (4 channel) 24-bit Left Justified (SCLK must be at least 128Fs for this mode) (Configuration of AUDATA3 as S/PDIF (IEC60958) or Digital Audio in the format of I2S or Left Justified is covered in AN162 and AN163) 0x80027F 0xFC7FFF 0x80017F 0x010000 0x80027C 0xF01F00 B Value DAO Data Format Of AUDATA0, 1, 2 (or AUDATA0 for Multichannel Modes) Hex Message Table 23. Output Data Format Configuration (Parameter B) (Continued) C Value MCLK Frequency Hex Message 0 (default) 256Fs 0x80027F 0xFFE7FF 1 512Fs 0x80027F 0xFFE7FF 0x80017F 0x001000 2 128Fs 0x80027F 0xFFE7FF 0x80017F 0x001800 3 384Fs (SCLK must be 64Fs in this mode and MCLK must be an input) 0x80027F 0xFFE7FF 0x80017F 0x000800 Table 24. Output MCLK Configuration (Parameter C) D Value SCLK Frequency Hex Message 0 (default) 64Fs 0x80027F 0xFFF8FF 0x80017F 0x000100 1 128Fs 0x80027F 0xFFF8FF 0x80017F 0x000200 2 256Fs 0x80027F 0xFFF8FF 0x80017F 0x000300 Table 25. Output SCLK Configuration (Parameter D) E Value SCLK Polarity Hex Message 0 (default) Data Valid on Rising Edge (clocked out on falling) 0x80027F 0xF7FFFF 1 Data Valid on Falling Edge (clocked out on rising) 0x80017F 0x080000 Table 26. Output SCLK Polarity Configuration (Parameter E) |
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