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L99PD08 データシート(PDF) 12 Page - STMicroelectronics

部品番号 L99PD08
部品情報  SPI control diagnosis interface device for VIPower M0-5 and M0-5E high side drivers
PDF  41 Pages
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メーカー  STMICROELECTRONICS [STMicroelectronics]
ホームページ  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

L99PD08 データシート(HTML) 12 Page - STMicroelectronics

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Device mode
L99PD08
12/41
Doc ID 15872 Rev 3
3
Device mode
Note:
To leave FAIL SAVE the LHOMEN-bit in ControlRegister (Addr.: hex00, Bit 0) has to be set
to ‘1’. FAIL SAVE is reentered by either ChipSelectNot-TimeOut (CSNTO) or SW-Reset (in
both cases LHOME-bit is automatically reset) or setting this bit to ‘0’ via SPI access.
To stay in normal mode a rising edge has to be generated at CSN within every timeframe
programmed in the control register (Addr.: hex00, Bit 3,2). Else a CSNTO is detected and
FAIL SAVE entered.
When SDI is stuck to GND the device enters automatically FAIL SAVE.
When SDI is stuck to logical high level then the device receives a SW-Reset and enters FAIL
SAVE. A read of ROM address Addr.: hex3F is detected as stuck to logical high level.
In FAIL SAVE the SYNC pin is logical high.
Table 3.
Device modes
Mode
Source
Actions
CS-timer
SPI state
Outputs
state
ChipReset-
bit
LHOMEN
Power down
Low VCORE3
All registers
are cleared
Not active
No comm.
High-Z
fail safe
1LOW(1)
Standby
EN = ‘0’
All registers
are cleared
Not active
No comm.
High-Z
fail safe
1LOW(1)
Fail save
CSNTO(2) /
LHOMEN bit =‘0’
-
Active
Active
High-Z
fail safe
0
LOW(1)
SW reset
All registers
are cleared
1
Normal
LHOMEN-bit = ‘1’
-
Active
Active
Normal
0
VDDIO
1. Max. sink current can only be guaranteed for VCORE3 VCORE3min. Therefore an external pull down is recommended.
2. ChipSelectNot-TimeOut



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