PIC16F707T-ESLASHML datasheet(44/284 Pages) MICROCHIP

44 / 284 page

PIC16F707/PIC16LF707

DS41418A-page 44

Preliminary

 2010 Microchip Technology Inc.

4.5.3

PIE2 REGISTER

The PIE2 register contains the interrupt enable bits, as

shown in Register 4-3.

Note:

Bit PEIE of the INTCON register must be

set to enable any peripheral interrupt.

PIE2 – PERIPHERAL INTERRUPT ENABLE REGISTER 2

R/W-0

U-0

R/W-0

TMR3GIE

TMR3IE

TMRBIE

TMRAIE

—

CCP2IE

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

u = bit is unchanged

x = Bit is unknown

-n/n = Value at POR and BOR/Value at all other

Resets

‘1’ = Bit is set

‘0’ = Bit is cleared

bit 7

TMR3GIE: Timer3 Gate Interrupt Flag bit

1 = Enable the Timer3 gate acquisition complete interrupt

0 = Disable the Timer3 gate acquisition complete interrupt

bit 6

TMR3IE: Timer3 Overflow Interrupt Enable bit

1 = Enables the Timer3 overflow interrupt

0 = Disables the Timer3 overflow interrupt

bit 5

TMRBIE: TimerB Overflow Interrupt Enable bit

1 = Enables the TimerB interrupt

0 = Disables the TimerB interrupt

bit 4

TMRAIE: TimerA Overflow Interrupt Enable bit

1 = Enables the TimerA interrupt

0 = Disables the TimerA interrupt

bit 3-1

Unimplemented: Read as '0'

bit 0

CCP2IE: CCP2 Interrupt Enable bit

1 = Enables the CCP2 interrupt

0 = Disables the CCP2 interrupt

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