PIC16F707T-ESLASHML datasheet(96/284 Pages) MICROCHIP

96 / 284 page

PIC16F707/PIC16LF707

DS41418A-page 96

Preliminary

 2010 Microchip Technology Inc.

12.1

Timer0 Operation

The Timer0 module can be used as either an 8-bit timer

or an 8-bit counter.

12.1.1

8-BIT TIMER MODE

The Timer0 module will increment every instruction

cycle, if used without a prescaler. 8-bit Timer mode is

selected by clearing the TMR0CS bit of the OPTION

When TMR0 is written, the increment is inhibited for

two instruction cycles immediately following the write.

12.1.2

8-BIT COUNTER MODE

In 8-bit Counter mode, the Timer0 module will increment

on every rising or falling edge of the T0CKI pin. 8-bit

Counter mode using the T0CKI pin is selected by setting

the TMR0CS bit of the OPTION register to ‘1’.

The rising or falling transition of the incrementing edge

for either input source is determined by the TMR0SE bit

in the OPTION register.

12.1.3

SOFTWARE PROGRAMMABLE

PRESCALER

A single software programmable prescaler is available

for use with either Timer0 or the Watchdog Timer

(WDT), but not both simultaneously. The prescaler

assignment is controlled by the PSA bit of the OPTION

must be cleared to a ‘0’.

There are 8 prescaler options for the Timer0 module

ranging from 1:2 to 1:256. The prescale values are

selectable via the PS<2:0> bits of the OPTION register.

In order to have a 1:1 prescaler value for the Timer0

module, the prescaler must be assigned to the WDT

module.

The prescaler is not readable or writable. When the

prescaler is enabled or assigned to the Timer0 module,

all instructions writing to the TMR0 register will clear the

prescaler.

12.1.4

TIMER0 INTERRUPT

Timer0 will generate an interrupt when the TMR0

interrupt flag bit of the INTCON register is set every

time the TMR0 register overflows, regardless of

whether or not the Timer0 interrupt is enabled. The

TMR0IF bit can only be cleared in software. The

Timer0 interrupt enable is the TMR0IE bit of the

INTCON register.

12.1.5

USING TIMER0 WITH AN

EXTERNAL CLOCK

When Timer0 is in Counter mode, the synchronization

of the T0CKI input and the Timer0 register is

accomplished by sampling the prescaler output on the

Q2 and Q4 cycles of the internal phase clocks.

Therefore, the high and low periods of the external

clock source must meet the timing requirements as

shown in Section 25.0 “Electrical Specifications”.

12.1.6

TIMER ENABLE

Operation of Timer0 is always enabled and the module

will operate according to the settings of the OPTION

12.1.7

OPERATION DURING SLEEP

Timer0 cannot operate while the processor is in Sleep

mode. The contents of the TMR0 register will remain

unchanged while the processor is in Sleep mode.

Note:

The value written to the TMR0 register can

be adjusted, in order to account for the two

instruction cycle delay when TMR0 is

written.

Note:

When the prescaler is assigned to WDT, a

CLRWDT instruction will clear the prescaler

along with the WDT.

Note:

The Timer0 interrupt cannot wake the

processor from Sleep since the timer is

frozen during Sleep.

PIC16F707T-E/ML データシート(PDF) 96 Page - Microchip Technology

PIC16F707T-E/ML データシート(HTML) 96 Page - Microchip Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

データシートダウンロード

リンク URL

PIC16F707T-E/ML データシート(PDF) 96 Page - Microchip Technology

PIC16F707T-E/ML データシート(HTML) 96 Page - Microchip Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

データシート ダウンロード

リンク URL

データシートダウンロード