EM357-RTR datasheet(183/240 Pages) ETC2

183 / 240 page

EM351 / EM357

NVREF is a sampling of VREF. Due to the ADC's internal design, VREF does not yield the maximum positive

two’s complement 0x7FFF as the conversion result. Instead, VREF yields a two’s complement value close

to 0x2000 when the input buffer is not selected and yields a two’s complement value close to 0xF000 when

the input buffer is selected

NVREF/2 is a sampling of VREF/2. VREF/2 yields a two’s complement value close to 0x0000 when the input

buffer is not selected, and yields a two’s complement value close to 0xE800 when the input buffer is

selected.

Offset correction is affected by the gain correction value. Offset correction is calculated after gain

correction has been applied.

10.5

ADC Key Parameters

Table 10-6 describes the key ADC parameters measured at 25°C and VDD_PADS at 3.0 V, for a sampling clock

of 1 MHz. ADC_HVSELP and ADC_HVSELN are programmed to 0 to disable the input buffer. The single-ended

measurements were done at finput = 7.7% fNyquist; 0 dBFS level (where full-scale is a 1.2 V p-p swing). The

differential measurements were done at finput = 7.7% fNyquist; -6 dBFS level (where full-scale is a 2.4 V p-p

swing) and a common mode voltage of 0.6V.

Table 10-6. ADC Module Key Parameters for 1 MHz sampling

Parameter

Performance

ADC_PERIOD

Conversion Time (µs)

128

256

512

1024

2048

4096

Nyquist Freq (kHz)

15.6k

7.81k

3.91k

1.95k

977

488

244

122

3 dB Cut-off (kHz)

9.43k

4.71k

2.36k

1.18k

589

295

147

73.7

INL (codes peak)

0.083

0.092

0.163

0.306

0.624

1.229

2.451

4.926

INL (codes RMS)

0.047

0.051

0.093

0.176

0.362

0.719

1.435

2.848

DNL (codes peak)

0.028

0.035

0.038

0.044

0.074

0.113

0.184

0.333

DNL (codes RMS)

0.008

0.009

0.011

0.014

0.019

0.029

0.048

0.079

ENOB

(from single-cycle test)

5.6

7.0

8.6

10.1

11.5

12.6

13.0

13.2

10-8

120-035X-000D

Preliminary

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