5-22
RF2413
Rev B3 990419
5
Pin
Function
Description
Interface Schematic
1
VDD2
Supply Voltage for the RF Output Stage only. A 33pF external bypass
capacitor is required and an optional 0.1
µF will be required if no other
low frequency bypass capacitors are nearby. The trace length between
the pin and the bypass capacitors should be minimized. The ground
side of the bypass capacitors should connect immediately to ground
plane.
Though the part is designed to run from a 5V supply, it will work at 3V.
Gain and available output power will be reduced by 5 to 10dB. This also
means that the part is sensitive to unintended power supply variation.
Power supply voltage should be kept constant, or another way of main-
taining constant output power is required.
2
VDD1
Supply Voltage for all circuits except the RF Output Stage. The same
comments as for VDD2 apply to this pin.
3PD
Power Down control. When this pin is 0V all circuits are turned off, and
when this pin is VDD all circuits are operating. This is a high impedance
input, internally connected to the gates of a few FETs. To minimize cur-
rent consumption in power down mode, this pin should be as close to
0V as possible. Turn-on voltage of some parts of the circuit may be as
low as 0.1V. In order to maximize output power this pin should be as
close to VDD as possible during normal operation.
4I SIG
Baseband input to the I mixer. This pin is DC coupled. Maximum output
power is obtained when the input signal has a peak to peak amplitude
of 5V. The DC level supplied to this pin should be VDD2/2. Input imped-
ance of this pin is about 3k
Ω.
5I REF
Reference voltage for the I mixer. This voltage should be the same as
the DC voltage supplied to the I SIG pin. To obtain a carrier suppres-
sion of better than 25dB it may be tuned ±0.15V (relative to the I SIG
DC voltage). Without tuning it will typically be better than 25dB. Input
impedance of this pin is about 3k
Ω.
6Q REF
Reference voltage for the Q mixer. This voltage should be the same as
the DC voltage supplied to the Q SIG pin. To obtain a carrier suppres-
sion of better than 25dB it may be tuned ±0.15V (relative to the Q SIG
DC voltage). Without tuning, the carrier suppression will typically be
better than 25dB. The input impedance of this pin is about 3 k
Ω.
Same as pin 5.
7Q SIG
Baseband input to the Q mixer. This pin is DC coupled. Maximum out-
put power is obtained when the input signal has a peak to peak ampli-
tude of 5V. The DC level supplied to this pin should be VDD2/2. Input
impedance of this pin is about 3k
Ω.
Same as pin 4.
8GC1
Gain control of the IF input amplifier. This pin, when used as the only
gain control, will give a 30dB control range. When used together with
GC2, a 60dB range is available. When this pin is at 1.8V or lower, the
gain is set to the minimum; when this pin is at 3.8V or above, the gain is
set to the maximum; see the plot below for typical characteristics. If
fixed maximum output level is required, it is recommended to connect
this pin to VDD. There are no provisions in the chip for limiting the
bandwidth of the gain control, so very fast response times are avail-
able. If a slower response is desired, an external capacitor can be
added.
9GC2
Gain control for the RF output amplifier. This pin has the same control
characteristics as GC1.
Same as pin 8.
V
DD1
V
DD2
PD
I SIG
I REF
GCx
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