K6R1016V1D

CMOS SRAM

Revision 3.0

- 3 -

June 2002

for AT&T

64K x 16 Bit High-Speed CMOS Static RAM(3.3V Operating)

The K6R1016V1D is a 1,048,576-bit high-speed Static Random

Access Memory organized as 65,536 words by 16 bits.

The K6R1016V1D uses 16 common input and output lines and

has at output enable pin which operates faster than address

access time at read cycle. Also it allows that lower and upper

byte access by data byte control (UB, LB). The device is

fabricated using SAMSUNG

′s advanced CMOS process and

designed for high-speed circuit technology. It is particularly well

suited for use in high-density high-speed system applications.

The K6R1016V1D is packaged in a 400mil 44-pin plastic SOJ

or TSOP2 forward or 48-TBGA.

GENERAL DESCRIPTION

FEATURES

• Fast Access Time 8,10ns(Max.)

• Low Power Dissipation

Standby (TTL)

: 20mA(Max.)

(CMOS) :

5mA(Max.)

Operating

K6R1016V1D- 08: 80mA(Max.)

K6R1016V1D-10: 65mA(Max.)

• Single 3.3V Power Supply

• TTL Compatible Inputs and Outputs

• Fully Static Operation

- No Clock or Refresh required

• Three State Outputs

• Center Power/Ground Pin Configuration

• Standard Pin Configuration:

K6R1016V1D-J: 44-SOJ-400

K6R1016V1D-T: 44-TSOP2-400BF

K6R1016V1D-E: 48-TBGA ( 6.0mm X 7.0mm )

with 0.75mm ball pitch

• Operating in Commercial and Industrial Temperature range.

Clk Gen.

OE

UB

CS

FUNCTIONAL BLOCK DIAGRAM

Data

Cont.

Column Select

CLK

Gen.

Pre-Charge Circuit

Memory Array

512 Rows

128x16 Columns

I/O Circuit &

Data

Cont.

WE

LB

PIN FUNCTION

Pin Name

Pin Function

Address Inputs

WE

Write Enable

CS

Chip Select

OE

Output Enable

LB

UB

Data Inputs/Outputs

Power(+3.3V)

Ground

N.C

No Connection