SST25WF080 datasheet(21/29 Pages) SST

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Advance Information

8Mbit 1.8V SPI Serial Flash

SST25WF080

S71203-03-000

04/10

Power-Up Specifications

All functionalities and DC specifications are specified for a VDD ramp rate of greater than 1V per 100 ms (0V to 1.8V

in less than 180 ms). If the VDD ramp rate is slower than 1V/100 ms, a hardware reset is required. The recom-

mended VDD power-up to RESET# high time should be greater than 100 µs to ensure a proper reset. See Table 9

and Figures 25 and 26 for more information.

FIGURE 25: Power-Up Reset Diagram

TABLE

9: Recommended System Power-up Timings

Symbol

Parameter

Minimum

Units

TPU-READ1

1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

VDD Min to Read Operation

100

µs

TPU-WRITE1

VDD Min to Write Operation

100

µs

T9.0 1203

1203 F37.0

VDD

RESET#

CE#

TPU-READ

VDD min

VIH

TRECR

Note: See Table 2 on page 5 for TRECR parameter.

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