STW4811MBRATSLASHLF datasheet(16/85 Pages) STMICROELECTRONICS

16 / 85 page

Functional description

STw4811M/STw4811N

16/85

CD00131784

REQUEST_MC ball. STw4811 remains in internal oscillator mode until it receives the

external clock signal on MASTER_CLK ball (optional).

EXT_CLK: if MASTER_CLK is used, when detected, the STw4811 uses this clock as

reference and switches off its internal oscillator. MASTERCLK should remain connected up

to sleep mode.

SLEEP: sleep mode is required by multimedia processor by setting a PWREN at low level.

Then VDDOK is forced to 0, regulators (VCORE, VIO_VMEM) switch to sleep mode and

wait for PWREN at high level (

Figure 4).

WAKE-UP: from sleep mode, the multimedia processor requests to switch back to high

power mode. Thus the device restarts its internal oscillator and then switches regulators

from SLEEP to high power mode and informs multimedia processor with VDDOK at high

level (

Figure 4).

Note:

The default state of VAUX is different for STw4811M and for STw4811N.

- VAUX default state is OFF at start up for STw4811M.

- VAUX default state is ON at start up for STw4811N.

VAUX can be programmed in high power mode only by asserted pdn_vaux bit to “1”

(Table 18).

If MASTER_CLK is used instead of internal oscillator all the features are not supported in

sleep mode (see Section 4.2.3).

STW4811MBRAT/LF データシート(PDF) 16 Page - STMicroelectronics