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STM8L101F1P3ATR データシート(PDF) 33 Page - STMicroelectronics |
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STM8L101F1P3ATR データシート(HTML) 33 Page - STMicroelectronics |
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33 / 81 page  STM8L101xx Interrupt vector mapping Doc ID 15275 Rev 11 33/81 27 USART Transmission complete/transmit data register empty -- Yes Yes(1) 0x00 8074 28 USART Receive Register DATA FULL/overrun/idle line detected/parity error -- Yes Yes(1) 0x00 8078 29 I2C I2C interrupt(2) Yes Yes Yes Yes(1) 0x00 807C 1. In WFE mode, this interrupt is served if it has been previously enabled. After processing the interrupt, the processor goes back to WFE mode. Refer to SectionWait for event (WFE) mode in the RM0013 reference manual. 2. The device is woken up from Halt or Active-halt mode only when the address received matches the interface address. Table 9. Interrupt mapping (continued) IRQ No. Source block Description Wakeup from Halt mode Wakeup from Active-halt mode Wakeup from Wait (WFI mode) Wakeup from Wait (WFE mode) Vector address |
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