IMX53CEC datasheet(65/204 Pages) FREESCALE

部品番号	IMX53CEC

部品情報	Applications Processors for Consumer Products

PDF	204 Pages

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メーカー	FREESCALE [Freescale Semiconductor, Inc]

ホームページ	http://www.freescale.com

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Electrical Characteristics

i.MX53xD Applications Processors for Consumer Products, Rev. 2

Freescale Semiconductor

4.6.7

DDR SDRAM Specific Parameters (DDR2/LVDDR2, LPDDR2, and

DDR3)

The DDR2/LVDDR2 interface fully complies with JESD79-2E – DDR2 JEDEC release April, 2008,

supporting DDR2-800 and LVDDR2-800.

The DDR3 interface fully complies with JESD79-3D – DDR3 JEDEC release April 2008 supporting

DDR3-800.

The LPDDR2 interface fully complies with JESD209-2B, supporting LPDDR2-800.

Figure 28 and Table 41 show the address and control timing parameters for DDR2 and DDR3.

Figure 28. DDR SDRAM Address and Control Parameters for DDR2 and DDR3

Table 41. DDR SDRAM Timing Parameter Table1 2

Parameter

Symbol

SDCLK = 400 MHz

Units

Min

Max

DDR1

SDRAM clock high-level width

tCH

0.48

0.52

tCK

DDR2

SDRAM clock low-level width

tCL

0.48

0.52

tCK

SDCLK

ADDR

ROW/BA

COL/BA

CAS

RAS

DDR1

DDR2

DDR4

DDR5

DDR6

DDR7

SDCLK

ODT/CKE

DDR4

IMX53CEC データシート(PDF) 65 Page - Freescale Semiconductor, Inc

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