データシートサーチシステム
  Japanese  ▼
ALLDATASHEET.JP

X  

Preview PDF HTML

CY14MB064J データシート(PDF) 6 Page - Cypress Semiconductor

部品番号 CY14MB064J
部品情報  64-Kbit (8 K x 8) Serial (I2C) nvSRAM Nonvolatile STORE/RECALL
PDF  31 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
メーカー  CYPRESS [Cypress Semiconductor]
ホームページ  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

CY14MB064J データシート(HTML) 6 Page - Cypress Semiconductor

Back Button CY14MB064J Datasheet HTML 2Page - Cypress Semiconductor CY14MB064J Datasheet HTML 3Page - Cypress Semiconductor CY14MB064J Datasheet HTML 4Page - Cypress Semiconductor CY14MB064J Datasheet HTML 5Page - Cypress Semiconductor CY14MB064J Datasheet HTML 6Page - Cypress Semiconductor CY14MB064J Datasheet HTML 7Page - Cypress Semiconductor CY14MB064J Datasheet HTML 8Page - Cypress Semiconductor CY14MB064J Datasheet HTML 9Page - Cypress Semiconductor CY14MB064J Datasheet HTML 10Page - Cypress Semiconductor Next Button
Zoom Inzoom in Zoom Outzoom out
 6 / 31 page
background image
CY14MB064J
CY14ME064J
Document #: 001- 65051 Rev. *B
Page 6 of 31
High Speed Mode (Hs-mode)
In Hs-mode, nvSRAM can transfer data at bit rates of up to
3.4 Mbit/s. A master code (0000 1XXXb) must be issued to place
the device into high speed mode. This enables master/slave
communication for speed upto 3.4 MHz. A stop condition exits
Hs-mode.
Serial Data Format in Hs-mode
Serial data transfer format in Hs-mode meets the standard-mode
I2C-bus specification. Hs-mode can only commence after the
following conditions (all of which are in F/S-modes):
1. START condition (S)
2. 8-bit master code (0000 1XXXb)
3. No-acknowledge bit (A)
Single and multiple-byte reads and writes are supported. After
the device enters into Hs-mode, data transfer continues in
Hs-mode until stop condition is sent by master device. The slave
switches back to F/S-mode after a STOP condition (P). To
continue data transfer in Hs-mode, the master sends Repeated
START (Sr).
See Figure 13 on page 11 and Figure 16 on page 12 for Hs-mode
timings for read and write operation.
Figure 6. Acknowledge on the I2C Bus
handbook, full pagewidth
S
START
condition
9
8
2
1
clock pulse for
acknowledgement
not acknowledge (A)
acknowledge (A)
DATA OUTPUT
BY MASTER
DATA OUTPUT
BY SLAVE
SCL FROM
MASTER
Figure 7. Data transfer format in Hs-mode
handbook, full pagewidth
F/S-mode
Hs-mode
F/S-mode
AA
/
A
A
DATA
n (bytes
+ack.)
W
/
R
S
MASTER CODE
Sr SLAVE ADD.
Hs-mode continues
Sr SLAVE ADD.
P
[+] Feedback



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31


データシート ダウンロード

Go To PDF Page


リンク URL



ALLDATASHEETはお客様のビジネスに役立ちますか？  [ DONATE ] 

Alldatasheetは   |   広告   |   お問い合わせ   |   プライバシーポリシー   |   データシートへのリンク    |   リンク交換   |   メーカーリスト
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com