CY14MB064J datasheet(8/31 Pages) CYPRESS

8 / 31 page

CY14MB064J

CY14ME064J

Document #: 001- 65051 Rev. *B

Page 8 of 31

Memory Control Register

The Memory Control Register contains the following bits:

■ BP1:BP0: Block Protect bits are used to protect 1/4, 1/2 or full

memory array. These bits can be written through a write

instruction to the 0x00 location of the Control Register Slave

device. However, any STORE cycle causes transfer of SRAM

data into a nonvolatile cell regardless of whether or not the

block is protected. The default value shipped from the factory

for BP0 and BP1 is ‘0’.

SNL (S/N Lock) Bit: Serial Number Lock bit (SNL) is used to lock

the serial number. Once the bit is set to ‘1’, the serial number

registers are locked and no modification is allowed. This bit

cannot be cleared to ‘0’. The serial number is secured on the next

STORE operation (Software STORE or AutoStore). If AutoStore

is not enabled, user must perform the Software STORE

operation to secure the lock bit status. If a STORE was not

performed, the serial number lock bit will not survive the power

cycle. The default value shipped from the factory for SNL is ‘0’.

Command Register

The Command Register resides at address “AA” of the Control

Registers Slave device. This is a write only register. The byte

written to this register initiates a STORE, RECALL, AutoStore

Enable, AutoStore Disable and sleep mode operation as listed in

Table 5. Refer to Serial Number on page 16 for details on how to

execute a command register byte.

■ STORE: Initiates nvSRAM Software STORE. The nvSRAM

cannot be accessed for tSTORE time after this instruction has

been executed. When initiated, the device performs a STORE

operation regardless of whether a write has been performed

since the last NV operation. After the tSTORE cycle time is

completed, the SRAM is activated again for read/write

operations.

■ RECALL: Initiates nvSRAM Software RECALL. The nvSRAM

cannot be accessed for tRECALL time after this instruction has

been executed. The RECALL operation does not alter the data

in the nonvolatile elements. A RECALL may be initiated in two

ways: Hardware RECALL, initiated on power-up; and Software

RECALL, initiated by a I2C RECALL instruction.

■ ASENB: Enables nvSRAM AutoStore. The nvSRAM cannot be

accessed for tSS time after this instruction has been executed.

This setting is not nonvolatile and needs to be followed by a

manual STORE sequence if this is desired to survive power

cycle. The part comes from the factory with AutoStore Enabled.

■ ASDISB: Disables nvSRAM AutoStore. The nvSRAM cannot

be accessed for tSS time after this instruction has been

executed. This setting is not nonvolatile and needs to be

followed by a manual STORE sequence if this is desired to

survive the power cycle.

Note If AutoStore is disabled and VCAP is not required, it is

required that the VCAP pin is left open. VCAP pin must never be

connected to ground. Power-Up RECALL operation cannot be

disabled in any case.

■ SLEEP: SLEEP instruction puts the nvSRAM in a sleep mode.

When the SLEEP instruction is registered, the nvSRAM

performs a STORE operation to secure the data to nonvolatile

memory and then enters into sleep mode. Whenever nvSRAM

enters into sleep mode, it initiates non volatile STORE cycle

which results in losing an endurance cycle per sleep command

execution. A STORE cycle starts only if a write to the SRAM

has been performed since the last STORE or RECALL cycle.

Table 2. Control Registers map

Address

Description Read/Write

Details

0x00

Memory

Control

Read/Write Contains Block

Protect Bits and Serial

Number Lock bit

0x01

Serial Number

8 Bytes

Read/Write

(Read only

when SNL

is set)

Programmable Serial

Number. Locked by

setting the Serial

Number lock bit in the

Memory Control

0x02

0x03

0x04

0x05

0x06

0x07

0x08

0x09

Device ID

Read only Device ID is factory

programmed

0x0A

0x0B

0x0C

0x0D

Reserved

Reserved Reserved

0xAA

Command

Write only Allows commands for

STORE, RECALL,

AutoStore

Enable/Disable,

SLEEP Mode

Table 3. Memory Control Register Bits

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

0SNL

(0)

BP1

(0)

BP0

(0)

Table 4. Block Protection

Level

BP1:BP0

Block Protection

000

None

1/4

0x1800-0x1FFF

1/2

0x1000-0x1FFF

0x0000-0x1FFF

Table 5. Command Register bytes

Data Byte

[7:0]

Command

Description

0011 1100

STORE

STORE SRAM data to nonvolatile

memory

0110 0000

RECALL

RECALL data from nonvolatile

memory to SRAM

0101 1001

ASENB

Enable AutoStore

0001 1001

ASDISB

Disable AutoStore

1011 1001

SLEEP

Enter Sleep Mode for low power

consumption

[+] Feedback

CY14MB064J データシート(PDF) 8 Page - Cypress Semiconductor

CY14MB064J データシート(HTML) 8 Page - Cypress Semiconductor

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

データシートダウンロード